[t52]

a little off-topic: s/pdif input pulse transformers from scientific conversion were recommended to me. just made an inquiry to sc about their new SC947-02 "Super" and prices are as follows:
1-49pcs: US$16.50 each
50-99pcs: US$11.50 each
100+pcs: US$8.00 each

pretty expensive parts and more than 50% down when ordering 100pcs, anybody interested in a group buy? i hope it's allowed to ask such questions here

i'm 100% NOT interested in making business here, it's just that we could save $800 when ordering 100... and this company has no resellers/distributors so one has to place a direct order.

 

[Garbz]

I'm not sure what you mean but from a standard point of view option 1 is best for driving multiple loads in many applications.

There's nothing wrong or even crude about using a 3 terminal regualtor as a CSS infront of the TL431 shunt. That's exactly how I did it, and it works like a treat. Don't forget to add a cap between the reference and the anode: C3 in http://www.tnt-audio.com/clinica/reg..._noise3_e.html

Modular approaches are good. I have a connector to bypass my analogue section which I'll change soon. A good DIY project should allow for easy tweaking.

 

[t52]

again: done some extensive reading...

• Garbz you are right about the caps for the tl431 (A<->Vref), i had A and K swapped in my initial schem, so these are wrongly located between K and Vref, will change that (and value to 22uF also)!
• there is some controversial discussion goning on about adding series resistors on data/clock lines. i'll add these as 10.16mm through hole resistors on the pcb so one can use jumpers if desired. it would probably be best to use a fast scope and look at the actual slopes with different seris R in the finished circuit.
• just read the post at http://www.diyhifi.org/forums/viewto...er=asc&start=0 . then i went off the idea to use the input muxer of the cs8416, i'll go for a more sophisticated spdif input stage with unbalanced 75ohms rca input, 1:1 transformer and 2 gates of the 74hcu04. i thought of using 75ohms coax relais for the input switching. for good attenuation of the non-active inputs these should probably be terminated properly - needs more relais
  
  .
• there seems to be no consensus on which input transformer to use, obviously tight coupling seems to be important and that sounds sensible to me. i'll ask jocko over at diyhifi if these beasts could be diyed, what cores to use then, wire gauge and winding numbers etc...
• any suggestions on which connectors to use for the digital<->analog board connection? we only have 4 signals (Iout+/- for left and right) + ground to carry...
• still have to complete the reset circuitry, hope i'll have time for all this today evening.

thats all for now...

 

[mojo]

I'm no expert on digial audio, but this thread interests me.

I like the idea of using a buffer to eliminate jitter. Even if it were just a 16 word FIFO, I think it would be pretty effective. Essentially, all the jitter is moved to the clock in the DAC.

Would you even need to sync with the input clock? How far off in terms of frequency are the typical CPD/soundcard clocks? Would drift be enough to cause problems?

The USB idea sounds good too. Writing a sound card driver could be tricky, but many USB tranceiver chips support a simple RS232 emulation mode, or a clocked output mode. With that and a simple uproc to manage things, you could easily maintain a buffer. Rather than writing a sound card driver you could just write a (much simpler) WinAMP/Foobar plugin. I'd be happy to help on that front.

 

[Tenesu]

Quote:

Originally Posted by t52 again: done some extensive reading... -there is some controversial discussion goning on about adding series resistors on data/clock lines. i'll add these as 10.16mm through hole resistors on the pcb so one can use jumpers if desired. it would probably be best to use a fast scope and look at the actual slopes with different seris R in the finished circuit.

http://www.highfrequencyelectronics....1005_Seams.pdf discusses how to terminate high frequency digital lines. I don't think you should need them given that audio operates at fairly low frequencies and your traces should be short.

Quote:

Originally Posted by t52 -there seems to be no consensus on which input transformer to use, obviously tight coupling seems to be important and that sounds sensible to me. i'll ask jocko over at diyhifi if these beasts could be diyed, what cores to use then, wire gauge and winding numbers etc...

This pdf might help you out. It's short on technical info but it does have links to manufacturers of dedicated spdif transformers. http://www.cirrus.com/en/pubs/appNote/AN134REV5.pdf

Also, http://homepages.wmich.edu/~n0czarne/an18.pdf discusses layout of digital to analog circuitry on a pcb. It might help you out a bit.

 

[t52]

hi mojo

sorry, i guess i'll have to disappoint you - i decided to go forward with my initial design idea and do a dac with asrc. some very detailed info on asrc is available in this thread here:
http://www.diyaudio.com/forums/showt...5&pagenumber=1

i still have the asynchronous reclocking method on my mind (where we would use the buffer). the buffer alone is pretty useless because it would over/underrun if the clocks only differ slightly. imagine the source putting out exactly 44101 samples per second, and the dac running a word clock of 44100 hz. in case of a 16 word buffer (per channel) this would overrun after 16 seconds.
actually i have NO idea how much the difference between clocks is on average, my example would be a deviation of 0.0023 %. so if we want to use a buffer we MUST synchronize clocks.
synchronous reclocking reaches this goal by having a voltage controlled crystal oscillator that tracks the incoming clock with a precision oscillator. imho this approach is still prone to errors because the vcxo can not be stable at all - it needs to track the (unstable) source clock. possibly the error is small enough to stay unnoticed, probably depends on the pll update rate and update "smoothness".

the best approach is to use the same clock on data source and dac. the dac gets the low jitter clock, the clock for the source doesn't have to be ultimately jitter free, it just needs to be synchronous to the dac clock. read: it can be distributed, buffered and munged around in different ways that introduce jitter on the delivered data. reclocking the data with the low jitter dac clock right before it should remove the jitter.
the tas1020 can be run in a mode where it signals the computer "need more data" and so the buffer never over- or underruns. we then can draw data from the buffer at a stable, low jitter clock rate and feed it to a dac.

i had another idea how to achieve the desired goal - synchronize source clock to dac clock: use a soundcard with spdif out and replace the soundcard xo with the dac clock - obviously this only works if dac clock and soundcard clock are of the same frequency or multiples of 2...

but as i said: all put back for the moment, i want to get some hands on experience with dac chips etc. that all is still on my mind, some time in the future i want to have a bit-perfect dac that is a clock master to its source. only the implementation is not fixed yet

btw: just came home from my favourite cocktail bar, so no updates on the circuit today evening

 

[t52]

uhm skipped post of Tenesu, so i'll answer this as well:
i didn't speak of terminating lines, i spoke of series resistors in data/clock lines, mainly to relieve the hard slopes of high speed digital lines. there's the crux - hard edges on signal transitions make for a "good" digital signal, otoh these can create emi and all sorts of other problems . i'm really not sure at all, if to apply this technique. a good scope will probably help out here (ouch from my wallet)

regarding the spdif input trans: thanks for the info . i'll read that tomorrow... btw: 44.1kHz/16bit audio leads to about 2.8MHz on the spdif line, 192kHz/24bit is abt. 18.4MHz (!!!), so this is high frequency and should be treated like that (if i learned something from being an emc engineer some years ago: hf is a bitch, fullstop)

good night everybody

 

[Garbz]

Quote:

Originally Posted by t52 a little off-topic: s/pdif input pulse transformers from scientific conversion were recommended to me. just made an inquiry to sc about their new SC947-02 "Super" and prices are as follows.

What who said that? Not Joko I assure you. If he heard you mention SC transformers for S/PDIF he would go down on you like a ton of bricks.

Apparently they aren't very suitable a certain models from "Pulse" are better.

Quote:

Originally Posted by t52 again: done some extensive reading... just read the post at http://www.diyhifi.org/forums/viewto...er=asc&start=0 . then i went off the idea to use the input muxer of the cs8416, i'll go for a more sophisticated spdif input stage with unbalanced 75ohms rca input, 1:1 transformer and 2 gates of the 74hcu04. i thought of using 75ohms coax relais for the input switching. for good attenuation of the non-active inputs these should probably be terminated properly - needs more relais .

Did I post this earlier? http://www.diyhifi.org/forums/viewtopic.php?p=5707#5707 One of the benefits of this circuit is that the S/PDIF line becomes TTL and above all balanced. The CS8416's input mux can't actually mux a differential signal excpet I didn't realise this till after I built this input stage. I ummed and ahhed for a week trying to figure out how to properly impliment a input selector for a S/PDIF signal. Then it dawned on my every input runs through its own buffer. What if all the buffers not in use were simple switched off. As I already had a 3-8 line decoder running LEDs to show which input was on, that same logic signal was used once again with transistor switches to make sure only one buffer was active at the time.

Initially though this did not work as the signal leaked through the 10k feedback resistor on the buffer. However this was solved by simply running the signal through an unused terminal on the 74hcu04 with no feedback.

Quote:

any suggestions on which connectors to use for the digital<->analog board connection? we only have 4 signals (Iout+/- for left and right) + ground to carry...

There is 5 usually. I have not looked at the datasheet but if you will impliment some kind of opamp output stage and do not want to deal with DC offset then quite often there is a VCom line as well. This usually applies only to DACs which run from a single ended supply. Again I did not read the datasheet so I do not know for sure.

Quote:

i had another idea how to achieve the desired goal - synchronize source clock to dac clock: use a soundcard with spdif out and replace the soundcard xo with the dac clock - obviously this only works if dac clock and soundcard clock are of the same frequency or multiples of 2...

This is actually already implimented in the professional domain. They are called word sync inputs and I have seen several professional cd players and soundcards which have BNC terminals on the back for this purpose. Not quite sure on the standard though. But this is something I will definitly investigate for my next project.

 

[Tenesu]

Quote:

Originally Posted by t52 uhm skipped post of Tenesu, so i'll answer this as well: i didn't speak of terminating lines, i spoke of series resistors in data/clock lines, mainly to relieve the hard slopes of high speed digital lines. there's the crux - hard edges on signal transitions make for a "good" digital signal, otoh these can create emi and all sorts of other problems . i'm really not sure at all, if to apply this technique. a good scope will probably help out here (ouch from my wallet) regarding the spdif input trans: thanks for the info . i'll read that tomorrow... btw: 44.1kHz/16bit audio leads to about 2.8MHz on the spdif line, 192kHz/24bit is abt. 18.4MHz (!!!), so this is high frequency and should be treated like that (if i learned something from being an emc engineer some years ago: hf is a bitch, fullstop) good night everybody

Guess I misread your post regarding the resistors. If your intent isn't to use them for termination then I'd leave them off. I don't think the amount of EMI generated by a small dac would be very much and should be taken care of by using a metal case or shielding a non-metallic one. Trying to "round" edges of a digital signal is just asking for problems in my opinion.

Yeah, 18MHz is high frequency. I guess I'm just used to thinking that millimeter is "high" and lower is "low"

 

[mojo]

Quote:

Originally Posted by t52 synchronous reclocking reaches this goal by having a voltage controlled crystal oscillator that tracks the incoming clock with a precision oscillator. imho this approach is still prone to errors because the vcxo can not be stable at all - it needs to track the (unstable) source clock. possibly the error is small enough to stay unnoticed, probably depends on the pll update rate and update "smoothness".

Interesting. I wonder though, would it be better to have a totally fixed, accurate as possible clock and simply drop the occasional sample to maintain the correct sample rate? Let's say it's 1 sample per second, how would it sound? Worse than jitter?

 

[Garbz]

Dropping samples does not sound very audiophile IMHO and no pun intended. I'd be more inclined to track the incoming stream at a really low rate. Twice a second or something like that. Also make it a slow ramping adjustment so that the adjustment itself does not create jitter, then add a little buffer incase things go awall.

 

[t52]

hi all, here's an updated schematic of the dac:
http://xlhost.de/downloads/jh/dac3-schem2.png

i added a more advanced spdif input circuitry, could someone comment on this? again the question: what's your favourite spdif pulse transformer? we need a part that is pretty easy to source from almost everywhere though... (should be fixed before i begin the layout work)

for the digital<->analog section connectors i chose 25pin sub-d connectors, they come angled (90°), can be purchased with gold contact plating and have very good contacts from my experience. if someone wants to skip the connectors he is free to use jumper wires...

there are lots of voltage regulators that draw from the preregulated 9v power supply, should i add electrolytics next to each input of them? what value, 220u-470u seems reasonable to me.

the 220u value for the tl431s (connected between K and Vref) was chosen according to http://www.tnt-audio.com/clinica/reg...edance2_e.html , hope that's correct this way...

i removed all the series resistors in the digital lines, the seem vodoo to me and i can't really see how the should help despite ruining the slope of the signal. keeping these lines as short as possible makes more sense to me.

one last question: there are two dacs and the cs8421 that need to get the clock signal. what's the recommended way of distributing it? is it legal to use the Q/Qbar outs from the comparator like i did in this schematic? there has been a long thread on diyaudio on how NOT to distribute clocks, so far no one has posted HOW to do it

 

[Garbz]

The TL431s look right. On the input of each LMxxxx regulator read the datasheet. Often very small capacitance is all that is needed if the signal is already filtered. Running it from a pre-reg though may change this. I would be inclined to start with something small though.

I haven't the foggiest what is going on with that clock line. Unless the output clock of the CS8421 is flipped or is delayed by one clock length then the output should come from Q should it not? I am not sure on the workings of this.

 

[t52]

hey, i thought i'd post some images of my work-in-progress...

here's the schematic:
http://xlhost.de/downloads/jh/dac5r5_schem.png
i removed the clock circuit and decided to have it delivered from an outboard low noise clock still to be designed. connection should happen via a small piece of 100ohms twisted pair cable connected to K3.

some things are already routed on pcb, i routed from right to left (schematic wise) and stopped at the cs8416 receiver chip. maybe some layout gurus could comment on my work?!
for soldering i thought it might indeed be sensible to swap upper and lower layers and the components on them, so all the ssop chips would be easily accessible on the lower layer. lots of work though...

here's the images:
http://xlhost.de/downloads/jh/dac5r5_layout_all.png (2 layers, groundplane removed)
http://xlhost.de/downloads/jh/dac5r5_layout_up.png (upper layer w/ groundplane)
http://xlhost.de/downloads/jh/dac5r5_layout_down.png (lower layer)

 

[ezkcdude]

I'm not a guru, for sure, but I have been told that right angles in traces should be avoided.