[t52]

upsampling highend dac project

hi there!

i'm quite new here and first of all i have to admit that you guys here have a lovely forum going. lots of knowledge to read an what striked me most: there's no fear of using the latest chips, soldering smds etc...

i always had the opinion that with digital media the dac is the most critical part in a digital chain. before the dac everything looks just trivial - distinguishing 0 from 1 can hardly fail?! in fact i must deny that digital cables can influence the sound, IF:
any network jitter is removed right before the dac and a very stable clock must be either supplied by the data source or recovered from the data stream (spdif f.ex.).
as plls don't seem to do the job very well, there's one option left: asynchronous sample rate conversion.
when we're doing asrc, why not upsample to 192kHz and let one of the latest generation dac chips do the hard work and thus create some very nice dac with nearly absolute immunity to input jitter? thanks to the auto-locking of the cs8421 the spdif input could accept any sampling rate, if i'm not mistaken here...

in my mind is a chain that looks something like this:

(optional) pcm2902 usb -> spdif
cs8416 spdif muxer/receiver -> i2s out
cs8421 asrc, upsamples to 192khz, i2s out
2x pcm1794 in balanced mono config
i/v with opamps, balanced (possibly some latest generation ad8610?)
balanced -> unbalanced conversion
low pass filter (see below)

some more thoughts:
- good xo like the kwak clock directly on board
- do we need a digital filter chip between the asrc and the dacs?
- ideally the low pass filter should have a variable frequency that matches the input sampling rate, right? what rolloff is good practive here?
- of course every chip should have it's own low noise supply regulator(s), i like it when everything is on board

i fear because of the complexity and the power demands this thing is not for portable use

these is my fist collection of thoughts, i'd appreciate some input

 

[Garbz]

It's good to see some others here attempting more complicated projects like this.

You're right in assuming that digital cables and everything prior to the DAC is insignificant (short of a data error) to the sound if jitter can be totally eliminated. Unfortunately this is harder then it sounds. While my project did not use ASRC I ignored it mainly because of the endless criticism it receives on forums like diyaudio and diyhifi. While the use of ASRC does attenuate jitter it also adds a new jitter on a now different frequency. The end result while it can be pleasing to the ear is far from jitter immune, and still highly dependant on the input. I don't understand the detailed workings of the problem but ASRC has been discussed and rejected as a method of eliminating jitter by the brighter minds of other forums.

I chose for my DAC to try and reduce it's working jitter as much as possible, and as I learn more I see it is still not all it can be

The choice of input chip is a problem. I used the same CS8416 but since then I've seen plenty of measurments showing textbook implimentations of all crystal chips, and the CS8412 recovered the master clock more accurately then any other chips. Most believe this is a powersupply related issue (CS8414/6 uses 3.3V not 5V for clock recovery). There are however ways to get this chip to behave.

When picking a powersupply for the VA (dedicated PLL supply of CS8416) choose a regulator with excellent HF performance. I picked a TL431 shunt with an inductor on the input and ferrite bead on output. I also got an excellent improvement in performance when the S/PDIF input was transformer coupled, converted to differential, and then buffered to TTL voltage levels. http://www.diyhifi.org/forums/viewto...3c3d4415f#5707

Finally I modded my source for use with 75ohm bnc connectors and properly terminated both sides of a coax cable. So this effectively removes the cable as a source of jitter.

For the analogue filter, these are getting less and less relevant with each new generation of DAC chips. The PCM1792 has -130db of stopband attenuation. In theory you don't even need a low pass filter. In practice just choose values that keep the rolloff and phase angle at 0 around 20khz. I'd ballpark 50khz and finetune it from there in SPICE.

I am not sure how complicated you wish to make this project but so far the only method of reclocking that seems to get the nod from the digital gurus including Jocko Homo and Guido Tent is synchronous reclocking. http://members.chello.nl/~m.heijlige...tml/dactop.htm I found this project linked from Tentlab's site and even if you do not wish to follow their way they still provide a library of information when justifying their design choices which is well worth a read.

Lol as soon as you need to carry around a source and a DAC I don't think a project is portable anymore.

 

[t52]

first of all: this is planned as my reference dac and i don't mind it being a little more expensive and complex.

what i'm confused about is the extent to which plls vs. asrc attenuates jitter.
in a article found at diyaudio the author expresses the opinion that asrc is indeed the best way to remove/attenuate jitter. now what about havin a cs8416 AND a cs8421, the first has a pll on chip, to attenuate input jitter, the second would do the upsampling...

here's the link to the mentioned article on diyaudio:
http://www.diyaudio.com/forums/showt...5&pagenumber=1

seems that the first step in this project is to choose the jitter attenuation method(s) and then the actual implementation...

one last question: i wanted to have a dac that could receive any sample rate between 32k and 192k (96k upper limit is also acceptable). am i correct with my assumption that the cs8416 receives any sample rate and outputs the same sample rate i2s? also correct that the cs8421 can accept any sample rate when configured as input slave while the master output can always deliver 192k?

 

[t52]

hehe, pretty silent here, so i'll post along some more thoughts after an evening full of reading.

why am i so after jitter in the first place? well, just recently i made some pretty large steps forward with my chain. i had a yamaha surround receiver which was driven by spdif from my htpc, the speakers are homemade from an audax kit. the yamaha receiver was plain crap. soundstage extremely unfocused, tonal balance was horrible. i had some interesting hours when listening to the same speakers after first replacing the computer as source by my creative muvo v200. soundstage suddenly "snapped" into place. surprising!
the next surprise came when i ordered 2 sonic impact "class t" amps. after doing a max. 3 minute a-b listening the yamaha was disonnected an is waiting to be thrown into the bin.

some comparisons with different cd players i could get hold of i noticed one thing for sure: the best focus has the creative, it has beaten any other source i have listened to so far. obviously the unfocused sound stage mainly seems to com from jitter, why is the mp3 player so much better here? i suspect it's because this thing can run from one dedicated clock, no clock recovery necessary anywhere.

so we're back to the jitter topic.
it's measureable + sonic influence is proven = need to elimiate it.

so did my readings bring any news? yep, as far as i can see there are two options again:

1. use the usb interface and slave the pc to a usb transceiver like the ti tas1020.
pros: everything could be clocked from a low noise clock eliminating transport jitter
cons: needs special firmware AND windows/linux drivers, i'm no windows user so big problem here. i could probably get a special firmware going and develop a linux driver to prove it works, but this is not going to be a one weekend task i fear

big con: needs a pc, not everyone's liking - i could live with that

2. use synchronous reclocking like mentioned here:
http://members.chello.nl/~m.heijlige...tml/dactop.htm
cons: needs a vcxo, tied to one sampling freq, if you want the dac to accept various sampling rates, this is going to be complicated i guess.
pros: no hassle with the software here

there's "virtual" number 3 here, which would be my choice: implement this thing in silicon, together with a spdif receiver that fills a fixed size buffer. a software implemented tracking circuit could steer a vcxo by a dac-driven voltage output dependant on the buffer fill status. idelly the buffer should be quite big, i.e. have space for ~1s of audio data. at an average buffer fill status of 50% this could lead to an update of the vcxo voltage twice per second fter locking on. but enough of the dreaming...

guess i will some some nights over this

...and have a look at the tas 1020 development kit...

 

[Garbz]

PLLs do not attenuate jitter AFAIK. They are simply used for clock recovery. The CS8416 does however have some onboard jitter rejection circuitry, although rejection is hardly a word for what it does. This also leads into your next question. Since a PLL recovers the clock rate any clock rate can be used with it providing it is within the range of the receiver. E.g. My computer permanently outputs 96khz and my cdplayer 44.1khz. Switching between them works seemlessly and the receiver chip handles everything. The LRCLK, and BCLK outputs adjust themselves accordingly. I don't know what you mean with the master slave arrangment. If you mean that the CS8416 can receive any rate but the CS8421 will always sample it to 192khz than this is right.

Search for jitter test track on this forum. Someone uploaded a track provided by me from the Stereophile disc. It shows how audible jitter is to a 1khz sinewave, and it's nasty.

On the topic of the problem with multiple sampling rates. Do you really need multiple rates? CDs run at 44.1khz, DVD-As typically downsample to 44.1khz (at least about 3/4 of my collection does), and SACDs refuse to output on S/PDIF at all. Also given a decent DAC I prefer downsampling my high-end formats to using them through the multiplayer I have anyday. Plus given the lacklusture industry support for these standards I doubt it matters

. That's just an opinion though.

 

[SnoopyRocks]

It's nice to see someone who wants to tackle an ambitious project.

PLLs can attenuate jitter on the incoming clock. They typically have a lowpass loop characteristic that filters the incoming jitter. However, lowering the 3dB frequency of the PLL's loop filter to reduce the incoming jitter has other consequences that can be difficult to manage. One of the trade-offs is increased susceptibility to jitter on the PLL's own VCO. To get this sort of clock recovery to work well as a jitter attenuator is not a task reasonable for a hobbyist.

ASRCs are much simpler to implement, since all the work is done for you by the chip designers. All that's really required is a high quality reference clock, something that was necessary in the first place. ASRC's can have very low cutoff frequenies in the range of a few Hz, doing wonders for jitter attenuation.

More information about how ASRCs work can be found in: R. Adams and T. Kwan, A Stereo Asynchronous Digital Sample-Rate Converter for Digital Audio, IEEE JSSC, April '94. Figure 11 shows how well their (ADI) implementation filters 100ns rms of jitter.

IMO, an ASRC circuit approach is the clear-cut way to go for a hobbyist who wants to build somehting that works and isn't simply going to copy someone else's circuit. If it's inteded to be a starting point for delving into advanced topics, that's another matter.

 

[adolphe]

I don't really have much to say at the moment, but thought I'd show my support for this project. I've been wanting to do a *higher* end USB dac, but I've had other projects lined up before I get to that. I'll contribute how I can if you'd like, but my knowledge of digital design is quite limited. I have a little more (classroom) experience with analog filters.

If it's of interest, there's a thread going on at diyaudio about upsampling in the "ultimate high-end dac" thread. The people there are talking about digital stuff that is beyond me at the moment though.

One thing to say, wouldn't it be better to use the PCM2707 as the USB receiver and skip the (useless) conversion to S/PDIF and go straight to I2S?

-Scott

 

[t52]

hi adolphe!

thanks for your reply. i decided to put the tas1020 and the synchronous resampling methods back and first try the initial spdif rx -> asrc -> dac aproach with a good low noise clock and lots of regulators on board

i just finished the initial schematics of the digital section, but i'm to tired to post it as pics now... will do that tomorrow.

to your question regarding 2707 vs 2902: i thought it would be nice to use the inout muxer of the cs8416 receiver, for the first board there will probably only be a single chinch spdif input with pulse transformer.

good night

 

[ezkcdude]

Quote:

Originally Posted by t52 one last question: i wanted to have a dac that could receive any sample rate between 32k and 192k (96k upper limit is also acceptable). am i correct with my assumption that the cs8416 receives any sample rate and outputs the same sample rate i2s? also correct that the cs8421 can accept any sample rate when configured as input slave while the master output can always deliver 192k?

Sounds like you will end up using AD1896 for your ASRC, right? If that is the case, why the need for the VCXO? Just output a single frequency (maybe 96 kHz) and use a quality XO. That's what some others here are doing (ble0t and 00940 come to mind), and me too. I'm taking my time though, working on a power supply first.

DAC schematic: http://www.cellandtissue.com/ezdac/schematic.pdf

 

[t52]

hi ezkcdude, no i want to use the cs8421 as asrc.

to all:
i just made an image of the current schematics, up to now in finished the digital section. atm i have only one chinch s/pdif input to the cs8416.
if i want to use the muxer and control it by rxsel0/1, does anybody know of a convenient 4-push-button solution?

there are lots of regulators for the chips:
- 78S09 as preregulator for all reg102s
- reg102-33 + tl431 with 80mA ccs (7805) for the cs8416
- reg102-33 + reg102-25 for the cs8421
- 2x tl431 with 2x 80mA ccs (7805) for the clock generator
- reg102-33 for each pcm1794, digital section

i planned dc inputs of +/-15V for the digital supply.

all dc chip input pins are blocked with 100n ceramics, apart from the Va pin of the cs8416 which is blocked by 100n+1n following instructions in the datasheet. you will normally not see paralelled caps in my designs... all chip supplies are decoupled with beads.

i also added 22ohm series resistors for all data lines. when these split (bck, wck, data for pcm1794 f.ex., clock signal to cs8421 and 2x pcm1794) does one use n resistors or just one and split after the resistor? should the resistor(s) be placed close to signal source or sink?

hope to hear some answers, comments, etc...

ah: and here's the schematic

http://xlhost.de/downloads/jh/dac3-schem1.png

 

[t52]

forgot to mention one thing: all the reset inputs of the chips are not connected yet, what's the recommended way of releasing the reset on such a board? all chips at once, or step by step?
or ist the resistor to vdd, cap to ground approach just fine here?

 

[Garbz]

The absolutely ideal way is to use it as it's intended. A time delay relative to powerup to allow all voltage levels to reach the correct point. A simple resistor capacitor will usually do but if you're going to do it properly a watchdog chip is the way to go like the TPS3125. This is an earlier schematic of the receiver to my DAC. It's not current but the watchdog timer chip remains unchanged from this. http://www.garbz.com/amp/dac/final/receiver.pdf It basically waits till the powersupply reaches a trigger threshold and then releases the reset line.

Everything downstream from the CS8416 is connected to the NV/ERR pin via a saturated transistor switch. I found that if left to it's own devices certain DAC chips PCM1730 in my case produce a nasty ~12khz tone it doesn't get a signal after a long time. Connecting it to NV/ERR ensures that the DAC chips go back into reset mode when the CS8416 loses a signal lock. Signal get's locked and the DAC chips boot up and start their voodoo.

 

[t52]

actually i thought of "chaining" the reset lines also:
cs8416 error out -> cs8421 reset
cs8421 src_unlock out -> dacs reset

i'll add that together with a tps3125 today evening...

i guess i should add resistors in the reset lines from chip to chip also, right?

 

[Garbz]

That depends on the voltages and the currents. Haven't looked at it myself since the NV/ERR pin and the reset pin on my DAC were of opposite ... polarities. (not the right word but i'm having a brain meltdown). Eitherway I had to add a transistor to invert it.

 

[t52]

i tend to ask silly questions that i can answer for myself the next day round

the reset line is delivering dc most of the time, no rising or falling edges that have hf energy in them, so i think we don't need a resistor here.

what i'd still like to know is if we need two or one resistor when splitting signals up, like the data/bclk/wclk lines for the two dacs, i'll try a little ascii art to make it clear

Code:

[left]1. 2. ,---RRR---> out1 ,---> in >--o in >---RRR---o `---RRR---> out2 `--->[/left]

no objections agains my crude aproach on ccs with the 7805 and using the tl431 shunt reg directly?

another idea i had yesterday: i think it would be sensible to split digital and analog sections on the pcb also, by adding some sort of pcb connector right after the dacs and put the current outputs on there. this way we could have different i/v conversion approaches, etc...
i'll add two tl431 regs for the 5v analog supply of the dac chips and then do an initial layout of the board, let's see what the layout gurus have to say...