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REVIEW - Yulong Audio Sabre DA8 Reference DAC

Discussion in 'Dedicated Source Components' started by project86, Jul 19, 2013.
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  1. brunk

    The Sabre DAC uses the Phase Lock Loop to lock unto an incoming signal. For I2S,  it locks to the bitclock.

    DPLL Values: The DPLL bandwidth can be set to the following values: “lowest”, “low”, “medium-low”, “medium”, “medium-high”, “high”, “highest” and “best”; there is also a 128x setting which apparently multiplies the bandwidth values x128.

    The DPLL has adjustable bandwidth. Setting the bandwidth to its lowest value results in maximum jitter reduction. However if the bandwidth is “too low”, the DPLL will loose lock and you will hear dropouts. Thus the usable lowest bandwidth setting is one where no dropouts occur. I have done extensive testing with the different settings of the DPLL. Here is a summary on how it behaves:

    1. “Best” setting works all the time for everything

    1. “Lowest” works for SPDIF input but never works for I2S input except for a few exceptionally modded I2S devices. Thus the lowest setting depends on the input format

    1. The lowest setting depends on the incoming sample rate. The higher the sample rate, the higher the lowest setting

    1. The lowest setting will not work when the DAC is cold (right after power-0n). The “warm up” period is 15-30 minutes

    I wrote 3 posts on the DPLL describing its behavior further:

    1. Post 1: [link]
    2. Post 2: [link]
    3. Post 3: [link]

    Relation of dpll bandwidth setting in SPDIF and I2S

    Fidelix indicate that the DPLL bandwidth setting for I2S is 64x smaller than in SPDIF. This was confirmed by the manufacturer. So:

    1. “Lowest” is 64X smaller in I2S than “Lowest” in SPDIF (1/64 the same setting in SPDIF)
    2. “Low” is 32X smaller in I2S than “Lowest” in SPDIF
    3. “Mid-Low” is 16X smaller in I2S than “Lowest” in SPDIF
    4. “Mid” is 8X smaller in I2S than “Lowest” in SPDIF
    5. “Mid-High” is 4X smaller in I2S than “Lowest” in SPDIF
    6. “High” is 2X smaller in I2S than “Lowest” in SPDIF
    7. “Highest” is the same as “Lowest” in SPDIF

  2. DarKen23
  3. Andrew_WOT
    I've read it from here
    and here
  4. brunk
    Hmm, I wonder if you did the 8x oversampling yourself if it would bypass the FIR and go to the IIR. I'm also tempted to maybe add some Vishay nudes in the output stage. [​IMG] 
  5. Andrew_WOT
    BTW, there seems to be newer version of ASIO drivers available on amanero web site.
    Haven't tried them yet, use at own risk. [​IMG] 
    Never mind, doesn't work with Yulong.
  6. DarKen23
    Andrew, did you output encoding to "none", check the sample rate box and make sure all states "no change". Also to the right side, select "Source number of channels"
  7. DarKen23
  8. DarKen23
    I gotta admit Andrew, thats one handsome setup. 
  9. brunk
    Almost looks like they were made for eachother too, if it wasn't for the different milling process on the faceplates.
  10. DarKen23
    Yea, the foot print is identical or very very close. 
  11. Andrew_WOT
    Not a JRiver user.
  12. Andrew_WOT

    I believe it's standard half rack size. Also front plates plates on both have rounded corners, which I like, Conductor had sharp edges (sounded the same way too LOL).
  13. project86 Contributor
  14. mcullinan
    This may sound crazy but it seems that the upgrade to Mavericks on Mac has improved SQ with the Yulong DA8. Maybe Im just hearing things :wink:
    Love this DAC!
  15. Esprit
    Could be Mavericks
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