[brunk]

  And even better source for tech savvy.
http://hifiduino.wordpress.com/sabre32/
Essentially this is ASRC stage that can be disabled, or at least this is my reading of it.

TL;DR
 
DPLL SETTING

The Sabre DAC uses the Phase Lock Loop to lock unto an incoming signal. For I2S,  it locks to the bitclock.

DPLL Values: The DPLL bandwidth can be set to the following values: “lowest”, “low”, “medium-low”, “medium”, “medium-high”, “high”, “highest” and “best”; there is also a 128x setting which apparently multiplies the bandwidth values x128.

The DPLL has adjustable bandwidth. Setting the bandwidth to its lowest value results in maximum jitter reduction. However if the bandwidth is “too low”, the DPLL will loose lock and you will hear dropouts. Thus the usable lowest bandwidth setting is one where no dropouts occur. I have done extensive testing with the different settings of the DPLL. Here is a summary on how it behaves:

1. “Best” setting works all the time for everything

1. “Lowest” works for SPDIF input but never works for I2S input except for a few exceptionally modded I2S devices. Thus the lowest setting depends on the input format

1. The lowest setting depends on the incoming sample rate. The higher the sample rate, the higher the lowest setting

1. The lowest setting will not work when the DAC is cold (right after power-0n). The “warm up” period is 15-30 minutes

I wrote 3 posts on the DPLL describing its behavior further:

1. Post 1: [link]
2. Post 2: [link]
3. Post 3: [link]

Relation of dpll bandwidth setting in SPDIF and I2S

Fidelix indicate that the DPLL bandwidth setting for I2S is 64x smaller than in SPDIF. This was confirmed by the manufacturer. So:

1. “Lowest” is 64X smaller in I2S than “Lowest” in SPDIF (1/64 the same setting in SPDIF)
2. “Low” is 32X smaller in I2S than “Lowest” in SPDIF
3. “Mid-Low” is 16X smaller in I2S than “Lowest” in SPDIF
4. “Mid” is 8X smaller in I2S than “Lowest” in SPDIF
5. “Mid-High” is 4X smaller in I2S than “Lowest” in SPDIF
6. “High” is 2X smaller in I2S than “Lowest” in SPDIF
7. “Highest” is the same as “Lowest” in SPDIF

 

[DarKen23]

  Not a whole lot, but at least some info, this is ESS thing, not Yulong creation.
http://www.esstech.com/PDF/ES9018%20ES9012%20Product%20Brief.pdf

 

[Andrew_WOT]

I've read it from here

  OSF bypass [link]:  Bypasses the internal oversampling FIR filter and expects the data to be at 8X oversampling according to the datasheet.  The data is sourced directly to the IIR filter. (The DAC expects the incoming data at 8x FS because internally it applies an 8X oversampling when the oversampling is enabled). The next stage is the asynchronous sample rate conversion (the jitter eliminator) where the data is re-sampled to a higher rate still [link].  The “final” sample rate -the rate coming out of the ASRC is entirely determined by the master clock, and it is fixed at MClk/64 [574]. Thus for the 100MHz Buffalo, the resampled rate is 1.5625 MHz and for the 80 MHz Buffalo, the resampled rate is 1.25 MHz [link]
You can read my results on oversampling bypass here: [link]

and here
 

  Oversampling frequency of the ASRC
The asynchronous sample rate conversion (the jitter eliminator) the data is re-sampled to a higher rate [link].  The “final” sample rate -the rate coming out of the ASRC, is entirely determined by the master clock and it is fixed at MClk/64 [574].

1. For the 100MHz Buffalo, the resampled rate is 1.5625 MHz
2. For the 80 MHz Buffalo, the resampled rate is 1.25 MHz [link]

More on oversampling here: [link]

 

[brunk]

  I've read it from here
and here
 

Hmm, I wonder if you did the 8x oversampling yourself if it would bypass the FIR and go to the IIR. I'm also tempted to maybe add some Vishay nudes in the output stage. 

 

 

[Andrew_WOT]

BTW, there seems to be newer version of ASIO drivers available on amanero web site.
http://www.amanero.com/asio/
 
Haven't tried them yet, use at own risk.

 
 
Never mind, doesn't work with Yulong.

 

[DarKen23]

Andrew, did you output encoding to "none", check the sample rate box and make sure all states "no change". Also to the right side, select "Source number of channels"

 

[DarKen23]

 

[DarKen23]

 
 
 

I gotta admit Andrew, thats one handsome setup. 

 

[brunk]

  I gotta admit Andrew, thats one handsome setup. 

Almost looks like they were made for eachother too, if it wasn't for the different milling process on the faceplates.

 

[DarKen23]

 

  I gotta admit Andrew, thats one handsome setup. 

Almost looks like they were made for eachother too, if it wasn't for the different milling process on the faceplates.

Yea, the foot print is identical or very very close. 

 

[Andrew_WOT]

  Andrew, did you output encoding to "none", check the sample rate box and make sure all states "no change". Also to the right side, select "Source number of channels"

Not a JRiver user.

 

[Andrew_WOT]

 

 

  I gotta admit Andrew, thats one handsome setup. 

Almost looks like they were made for eachother too, if it wasn't for the different milling process on the faceplates.

Yea, the foot print is identical or very very close. 

I believe it's standard half rack size. Also front plates plates on both have rounded corners, which I like, Conductor had sharp edges (sounded the same way too LOL).

 

[project86]

 
I believe it's standard half rack size. Also front plates plates on both have rounded corners, which I like, Conductor had sharp edges (sounded the same way too LOL).

 
ZING!

 

[mcullinan]

This may sound crazy but it seems that the upgrade to Mavericks on Mac has improved SQ with the Yulong DA8. Maybe Im just hearing things
Love this DAC!

 

[Esprit]

Could be Mavericks