[DACLadder]

Yes. I was refering to the HE-2, not the Master 2H.

http://www.audio-gd.com/HE/HE-2/HE-2EN.htm

Oh yes, the HE-2. It was only sold in Asia I believe. thanks. 100kg shipping is off Kingwa's chart for rates!

 

[Jackula]

Both DACs are receiving a balanced digital signal from the Auralic’s Aries G1 Wireless Streaming Transport, a unit very positively reviewed for its ability to deliver a quality digital output, stripped of heaps of jitter. So the following DAC has its hard work already done and sophisticate

Even if your steamer is able to output very low jitter, unless its output is physically soldered to the DAC board, jitter will be reintroduced somewhere between your steamer and your DAC.

It's possible the two DACs are similarly voiced, however I've not come across two DACs that sounds identical with completely different designs, heck sometimes the sound is altered just by changing the solder.

More likely is there is some kind of bottleneck in your setup, I don't know what it is, could be anything from cabling to HRTF.

 

[FredA]

Yip, Conclusion was contradictory. Auralic’s Aries G1 is so good that there is no difference between DACs, amaizing!!!

I wrote the same few days ago when a person tried to argue that G1 connection was bringing no audible noise and based on this an assumption was made on a jitter-free transmission.

This is not only your experience, but is a part of a general knowledge, there are no exceptions. Jitter produce absolutely no noise on a digital silence, but products of intermodulation spread across the entire spectrum when music is playing. Details in the music can only show when jitter amount is below perceived level. Serial communication with embedded clock is jittery by a nature. A long cable, multiroom cable connection is adding more interference. I am afraid a passive splitter won't help much as reflections of the signal from another room will mix with on a splitter.

Good DACs have an internal jitter removal circuit which is usually done by PLL (Phase Controlled Loop). It has limitations, as attempting to maximise loop gain leads to occasional losss of synchronisation. The older equipment had a manual switch for increasing frequency range the PLL can achieve a lock to deal with cases when it happens. These days designers use more relaxed loop gain (meaning allowing more jitter). This is because there are other ways to deal with an issue. One solution is to use a separate clock line for the synchronisation of the clock when using S/PDIF, the other is I2S connection, but both work well only on short distances. The other one use a feedback packet clock synchronisation method, so far only implemented on the USB connection.

There a limited quantity of jitter that can be removed of course.

 

[Articnoise]

There a limited quantity of jitter that can be removed of course.

Yes but we also have phase noise which is even harder to remove

 

[Articnoise]

Even if your steamer is able to output very low jitter, unless its output is physically soldered to the DAC board, jitter will be reintroduced somewhere between your steamer and your DAC.

Please explain this?

 

[FredA]

Yes but we also have phase noise which is even harder to remove

For me, it’s two sides of the coin. without phase noise, there is no jitter. And the reverse statement. Jitter is expressed with different units (second) over a wide frequency range and is sort of a global figure. Phase noise is a density fonction and is expressed in db/hz, so is a harder to understand notion.

 

[DACLadder]

Phase noise is easier for me to relate to in audio . Just think of a 100Hz pure bass tone. If modulated by 10Hz/dBr phase noise clock means the pure 100Hz tone output is varying by +/-10Hz or 90 to 110 Hz (F# to A notes). 1Hz/dBr is extremely important as well for bass, imaging, space, and location.

Jitter is usually speced over a wide bandwidth. Harder to judge how jitter spec affects the sound output.

 

[Articnoise]

For me, it’s two sides of the coin. without phase noise, there is no jitter. And the reverse statement. Jitter is expressed with different units (second) over a wide frequency range and is sort of a global figure. Phase noise is a density fonction and is expressed in db/hz, so is a harder to understand notion.

Yes and no .

https://audiophilestyle.com/forums/topic...ent-963599

 

[sajunky]

Yes but we also have phase noise which is even harder to remove

These are actually mutually exclusive requirements. A trade must be chosen between low PLL bandwith (for the input jitter rejection) and minimising a reference/VCO fluctuations refered as a phase noise.

 

[FredA]

These are actually mutually exclusive requirements. A trade must be chosen between low PLL bandwith (for the input jitter rejection) and minimising a reference/VCO fluctuations refered as a phase noise.

Yep. Unless both the spdif and dac are synched with the same clock, which make a really significant difference!

One thing that seems not well understood is the actual phase noise figure. For instance, - 90dBc/hz at 1hz means the phase will fluctuate of - 90db for each interval of 1 hertz, the - 90dB being a fraction of the clock period, if i am not mistaken. So this means the overall phase will have the corresponding relative fluctuation component of the phase, occuring like a sinusidal noise of 1hz frequency. So the actual overall phase noise signal will be obtained by summing up infinitesimal frequency intervals between 0 and 20kz or more, each one adding a tiny sine contribution of correponding frequency. This is college level maths.

 

[sajunky]

Yep. Unless both the spdif and dac are synched with the same clock, which make a really significant difference!

One thing that seems not well understood is the actual phase noise figure. For instance, - 90dBc/hz at 1hz means the phase will fluctuate of - 90db for each interval of 1 hertz, the - 90dB being a fraction of the clock period, if i am not mistaken. So this means the overall phase will have the corresponding relative fluctuation component of the phase, occuring like a sinusidal noise of 1hz frequency. So the actual overall phase noise signal will be obtained by summing up infinitesimal frequency intervals between 0 and 20kz or more, each one adding a tiny sine contribution of correponding frequency. This is college level maths.

In a case of a synchronised frequency PLL is not needed. It requires a simple latch buffering. This is a biggest change in DI-20 and 2021 DAC models that PLL is not deployed on a certain type of USB transfer. It was not communicated with us, but I expect that the same is done on the S/PDIF synchronised with a clock input, as it is logical.

I am sorry, with my English skills I can't follow your interpretation. A figure shows is how 1kHz of VCO deviation have effect on the output aplitude. It is not linear, when offset from a carrier frequency is smaller, the amplitude variations are increasing. It is not shown for simplicity, but with a very high loop gain, a noise from a VCO clock can have a bigger effect on the output than from a source clock. These are pitfals of PLL, it neeeds a designer to optimise for both (my previous post). There is lot of publications on this issue, maybe look at this. See fig.2.

 

[FredA]

In a case of a synchronised frequency PLL is not needed. It requires a simple latch buffering. This is a biggest change in DI-20 and 2021 DAC models that PLL is not deployed on a certain type of USB transfer. It was not communicated with us, but I expect that the same is done on the S/PDIF synchronised with a clock input, as it is logical.

I am sorry, with my English skills I can't follow your interpretation. A figure shows is how 1kHz of VCO deviation have effect on the output aplitude. It is not linear, when offset from a carrier frequency is smaller, the amplitude variations are increasing. It is not shown for simplicity, but with a very high gain loop a noise from a VCO clock can have a bigger effect on the output than from a source clock. These are pitfals of PLL, it neeeds a designer to optimise for both (my previous post). There is lot of publications on this issue, maybe look at this. See fig.2.

I am not talking about plls or VC0s. Just of phase noise as specified for XOs and how to interpret the graph typically shown by XO makers like crystek. Like in this spec:


http://www.crystek.com/crystal/spec-sheets/clock/CCHD-575.pdf

 

[sajunky]

I am not talking about plls or VC0s. Just of phase noise as specified for XOs and how to interpret the graph typically shown by XO makers like crystek. Like in this spec:


http://www.crystek.com/crystal/spec-sheets/clock/CCHD-575.pdf

There is actually VCO inside. Here is some theory, design example and measurements.

 

[anroj]

Just put 50 hours on the Nimak acss (audio 5).

Already, it's at level that makes you smile. The first hours, it sounded too soft, lacked spatial cues and was a littly muddy. Bass extension was lacking too. Piano lacked sharpness.

Now, it's at a level that makes Nimak's statement as to it's the best in the world very plausible.

It fits the r7he like a glove. Textured, dynamic sound. More shades of grey, more color variations I did not know the recordings contained. A very black background. Silky treble. And very musical. Excellent presence throughout the spectrum. Splendid lower mid. And midrange in general. Really no flaw i can identify. Soundstaging/imaging also excellent.

So much so i asked Dubravko at Nimak to make me a 4-pin xlr version to use between the he9 and m3. Not that i need it, but what if things get even better... This will be tough.

This is great news! I ordered an Audio 5 and Dubravko shipped it out on Monday of this week so it should arrive soon. I'll be pairing it with an R7HE (2020) and an NFB-1. I can't use it to my preamp as it's the Vacuum HE1 XLR, which doesn't have ACSS inputs.

 

[FredA]

I did test it on heaphones. Made quite a difference!