[ppl]

Quote:

Originally Posted by SnoopyRocks The input impedance is being misinterpretted here. With closed loop operation, you cannot simply take the input impedance. In fact, the impedance seen looking into the opamp small, roughly (Z_f+Z_o)/A_o, where Z_f and Z_o are the feedback and OpAmp output impedances. A_o is the loop gain. The impedance seen by the DAC would be the parallel combination of the actual input impedance and this effective impedance, resulting in a small overall impedance.

this is true that your resultent impedence is what ever you design it to be however it is my understanding that a current output dac likes to see a real low AC impedance

 

[Clutz]

Quote:

Originally Posted by MegaMeee I'm sure he's busy doing at uni doing his job... I know i'm busy doing the assignments he has written

Off topic: Interesting. What course is are you taking? Is he a professor?

Cheers,
Clutz

 

[ble0t]

Ok, here's the 'final' version of the sch/brd. Obviously, minor fixes and tweaks are still an option, but any new additions/major changes are pretty much done. We've added an optional balanced output section that can be jumpered to from the pads following the I/V stage. For your viewing pleasure...

Schematic

Top Layer

Bottom Layer

Both Layers w/Silk

 

[98venom]

Is there a proposed group buy on this? I would seriously be interested in getting a board or two for a future project.......

 

[Clutz]

Deleted.

 

[MegaMeee]

Quote:

Originally Posted by Clutz Off topic: Interesting. What course is are you taking? Is he a professor? Cheers, Clutz

Im doing comp science and mechatronic engineering double.

As for Francis I don't have him for any lectures. The assignment I did that he wrote was a computer architecture assignment.
He's listed on the Uni of Adelaide website as an adjunct senior lecturer. From the Comp Science staff page we only have three "professors", those people being the heads and deputy heads of school. Most people on the academic side are listed as either senior lecturers or lecturers.

I'm guessing that he basically is the computer architecture guy at the Adelaide Uni, if that makes sense.

 

[Clutz]

Hi ble0t,

It looks good, very good, to me. Why are there through-hole resistors between the PCM2707 and the reclocker, and the CS8416 and the reclocker instead of SMD? Just to keep SMD count down?

How important do you expect the power supply to be? e.g. Will a tread be sufficient - or is something approaching a steps going to provide substantial improvements?


I'm really excited

Cheers,

Clutz

Quote:

Originally Posted by ble0t Ok, here's the 'final' version of the sch/brd. Obviously, minor fixes and tweaks are still an option, but any new additions/major changes are pretty much done. We've added an optional balanced output section that can be jumpered to from the pads following the I/V stage. For your viewing pleasure... Schematic Top Layer Bottom Layer Both Layers w/Silk

 

[00940]

The through hole resistors are actually there to allow you to easily connect alternative I2S inputs.

There is the equivalent of a tread onboard, so power supply shouldn't be too critical.

 

[Clutz]

Quote:

Originally Posted by 00940 The through hole resistors are actually there to allow you to easily connect alternative I2S inputs.

Ahh, very clever.

Quote:

There is the equivalent of a tread onboard, so power supply shouldn't be too critical.

Alright.

Anxiously awaiting when the boards are ready to go.

 

[SnoopyRocks]

Nice work.

Some comments:

spdif receiver
Is it too late to reconsider the SPDIF receiver chip choice? A PIC controller seems like an unnecessary complication. Hardware programming is preferable. Right?
(I must have been asleep when the change was made.

)

Differential outputs
It's nice to see this option added.

However, some more thought needs to go into the differential filtering though. The fundamental issue is that the filtering is not symmetric. To understand why, look at the location of Pads 3,4,9 & 10 (i.e. the location that the differential outputs are forwarded from). The positive input gets a first order LPF. While the negative input does get filtered also, it reduced by the loop gain. A solution would be to move Pads 3,4,9, & 10 to the other side of R10/R13 & R29/R31. This would leave no image reject filtering on the differential outputs. I think that, at the very least, capacitors should be added in parallel with R47, R48, R49, & R51, giving a first order LPF on the differential outputs. Let's think this through more carefully.

 

[00940]

Snoopy : don't we have a lpf anyway with C37, C40, C51, C53 ? Considering how high the first alias will appear, isn't sufficient actually ?

I agree it would be best to move the pads, to avoid assymetric interaction with the output lpf.

 

[ble0t]

I'll see what I can do about moving those pads...

As for the PIC, I personally think it makes the design easier and more flexible. There are many more options that can be explored and the actual board layout is simplified/improved greatly by using it. Don't be frightened by the programmable logic

 

[00940]

If the PIC's code is made available, anyone can easily program one using this kind of diy programmer : http://www.janson-soft.de/pic/pic.htm . This one can be greatly simplified for our use for example.

I did something similar for the at90s1200 but working on the parallel port. As long as you don't have to write the code, it's very easy.

 

[ble0t]

That is also why I went with a DIP package for the PIC...it makes it easy to program using a variety of cheap programmers out there. I do plan on releasing the code once it gets to a stable, working point.

 

[ble0t]

OK...the pads have been moved as per SnoopyRocks' suggestion. I tend to agree with 00940 on the LPF question...I believe we already have that covered as far as I can tell.

Are there any other design related issues to get into? Speak now or forever hold your peace