[Francis_Vaughan]

Alf, yes, there is some good improvement in some of the caps, and indeed C18 was the one I was referring to as sub-optimal. Actually around the IC the ground plane is OK, and the bypassing in that region is OK - although tweak-able still I bet. But the damage to the ground-plane everywhere else seems just plain odd. Getting a totally continuos ground-plan under the IC would be good however.

Why stop using the other side? It just seems weird to have moved so many traces onto the top side - where they cut up the ground-plane - for no good reason.

With the cut up ground-plane you invite all sorts of cross coupling and resonances and invite much disturbance of the ground.

For instance, there is a loop that starts at the IC ground-plane, heads down, left across the bottom of the design, up under the USB socket, up, past the 12 volt pin, around C15, right, under C14, under crystal and under the IC. This will pick up RF energy, and couple it into anything nearby, including the IC and the analog power trace. There are also long spindly bits of ground-plane with bits hanging off them that look for all the world like small capacitors and inductors teamed up.

 

[00940]

/edit

 

[Botch]

Hi Alf, good to see the updated board and I can see a lot of work has gone into it. Well done (I mean it)! We have definately improved the schematic but we need to keep at it with the layout. There has been some very good comments from Francis here and they should not be taken as criticism but ways of improving the end product.

Just looking at the layout I would like to add my suggestions/ideas. Think it is easier if I say where I would move things to but take these comments just as ideas only.

- What spacing do you have set for the ground plane? Looks very close to the tracks (note I don't have a lot of SMD experience so can not say what is should be). Maybe increasing the spacing a little will help remove the ground plane from places that it will not make a big difference too. Can anyone else with experience comment on this please.

- Remove C4. As we have C5 I can not see a need for it. Or does anyone have a problem with this?
- move the 12V pad to the top of the board out of the way. It just goes into IC3 so no need to have it where it is.
- maybe move all of the IC2 stuff up a bit, L1 to the left a bit etc. There is some space there
- shift D2 to the right and up a bit, maybe also C7 a little.

This gives us a bit more space to play with for the 3.3V regulation and to look at its ground paths.

Without having the layout in front of me to play with I'm just trying to visualise things. Have a play with these ideas and see how it goes.

- move C15 to the other side of the IC5 and rotate it 180°. This cap should be as close as possible to the ground pin on the IC5 to minimise loop distance to prevent introducing noise on the ground.
- rotate C13 it 180° (for reason above)
- possibly move R4 down to where R5 is to free up space. You have to run 3.3V down there anyway.
- Rotate C19 either 90°CCW or 180° and place the ground pad as close as possible to DGND.
- Move C18 and place the ground pad as close as possible to DGNDC.

Now we have to think a bit again.
- There is some space to move IC5 (and C13 & C15) to the left, possibly rotating it 90° (CW or CCW - see how it looks both ways). CCW may be better but have a play here, thinking about the ground paths also.
- C14 will move with IC5.
- If you move the IC5, maybe place C16 & C17 to the top of the crystal giving more space to layout supply and ground paths to the left of IC1.

Where is the 3.3V track running now? Do the ground paths for this supply have a direct path back from IC5? Can you see a way of removing the ground loop that Francis described in his last post?

While we are looking at it, you have a 3V3 wire pad. I assume this is for having an external 3.3V supply (nice idea btw). If that is the reason why not add an extra GND pad close to the IC5 ground. Could also add an extra GND pad for the 5V supply next to IC4 and have 2 external power supplies, overkill maybe but would be an interesting test.

Analog output. Have not had a really good look at this but the principle locating the ground pad of the decoupling caps as close as possible to the gnd pin of the IC may need attention (C20, C21, C22 & C23). Space it tight here also but give it a shot. Maybe also rotate C24 around for the ground pad to close to the IC1 ground pin.

Some of the grounds on the analog side also have a long loop back to the 5V supply. Would sending the output signals (VoutR & VoutL) to the bottom layer from IC1 with a via and routing to CL & CR improve this? Would it effect the output quality? Not sure here.

Wow, this started out a little post but I think I got carried away (I'm not trying to design your board - honest

). Better get back to work now.

Like I said these are just ideas to think about. Keep at it Alf, you will a happy man the day you get one of these boards in your hands.

Botch.

 

[Clutz]

Hey Alf,

I cannot comment on the design - I don't know nearly enough. I just wanted to let you know I'm really excited about this!

 

[Alf]

I had no time to spend on the project today. I will try to move some traces to the bottom layer to improve the ground. I will work on C18 too.


Botch: C4 cannot be removed. TPS6734 datasheet is very specific about this capacitor and its location. I will try your other suggestions.

 

[Botch]

Hi Alf,

don't rush over this.

You know with C4 it is is parallel with C5 so your capacitance probably not to spec anyway. Have a look at it.

Sorry about the big post before but just got looking at it and had ideas. You know how it happens.

I've printed out the latout and schematic and I'm trying to imagine how I would connect the grounds, especially in the power supply sections using a star ground method. Hmmm, try it out and see what you think.

Can we think about running some supply traces on the bottom layer to help out our ground plane? Especially the ones before we do the final 3.3V & 5V regulation?

The USB 5V, 12V and 9V traces are all candidates.

Just moving a few traces really starts to open the design up. We can now start to look at individual ground paths for the caps on each regulator now.

Time for bed.

Botch...

 

[Francis_Vaughan]

Need to be careful here. A star ground is the wrong answer in any circuit with RF signals running about.

The whole idea of a star ground is to avoid interference of one ground return signal by another. That is if you have a signal ground return sharing the same conductor as a power ground return, the tiny resistance in the ground conductor will cause any change in current in the power return to create a voltage drop that will appear on the signal return. So we don't let the returns share conduction paths.

With RF about this doesn't work anymore. The individual traces for the ground act as coupled antennae, and cheerfully make the interference worse, not better. A single solid ground-plane has the effect of confining the RF energy in the traces to the vicinity of the trace, effectively providing an automatic star ground that is always as perfect as possible. Whilst it might be argued that the solid ground plane might allow for some cross interference at low frequencies, if there are very large return currents about, in reality, in a low level, low power device like a DAC this isn't going to occur.

It is possible to argue for some separation in the ground-plane to avoid the most low level of disturbance from appearing in critical places - like the Vref and DAC grounds. But it is very difficult to manage, and a trade-off that could only really be understood with RF simulation tools. (There is a possibility of making two very small cuts in a precise location under the IC, but that should only be considered as a controlled experiment after circuits are built.

 

[Botch]

I should have been clearer. I'm not proposing to use a star ground at all. I was just using it as an example of imagining the paths the return currents would take. Several of the power supply grounds have very long return paths with the current design. Maybe moving some of the supply traces to the bottom layer will help this.

It was late last night when I did the other post. What I wanted to say was clear in the head but....

Botch...

 

[Francis_Vaughan]

OK, indeed this is exactly the right approach.

 

[00940]

I was bored last night and couldn't sleep, so I came back to this old pcm2702. I tried to take some more care to decoupling, while preserving a decent groundplane on top. Certainly not a complete board but some food for thought.

(bigger )

(bigger )

 

[Alf]

Moving the supply traces to the bottom should not be a problem. My concern is that even if it is done, we still have a few thin ground traces around PCM2702 running between the signal traces and potentially causing interference as Francis suggested. There is no way around it. We can either disregard this or move the ground plane back to the bottom as in the original design.

 

[Alf]

Quote:

Originally Posted by 00940 I was bored last night and couldn't sleep, so I came back to this old pcm2702. I tried to take some more care to decoupling, while preserving a decent groundplane on top. Certainly not a complete board but some food for thought.

Nice approach!

I agree that we should use less SMD components on the top layer. This can be achieved in two ways:
* Move some SMD components to the bottom
* Replace some SMDs with their through-the-hole equivalents.

 

[Botch]

Quote:

Originally Posted by Alf Moving the supply traces to the bottom should not be a problem. My concern is that even if it is done, we still have a few thin ground traces around PCM2702 running between the signal traces and potentially causing interference as Francis suggested. There is no way around it. We can either disregard this or move the ground plane back to the bottom as in the original design.

I have something to try for this off the top of my head.

Looking at the analog section supplies and thier coupling caps. If you move the vias for the 5V from under IC1 to the right of the chip you have a nice gound under the IC now (Francis hinted at this in a previous post). Wire the ground pins directly to under the chip to this ground. Then position C20 to C23 (rotate 180° from current orientation) so thier gnd pad is as close to the ground pins as possible. This makes the ground track lengths as short as we can get them.

Drop the CR and CL signals to the bottom layer. Have the 5V coming in on vias for the analog supplies/coupling caps.

The position of R7 may have to go to the bottom, maybe.

Francis, could you please comment on this idea? Will having the analog ground running under the IC be a good solution here. Really busy at work today so not had a time to really think about this.

Botch...

 

[Francis_Vaughan]

00940 seems to have beaten you to the punch a little, but yes, this is exactly the right approach. The idea of swinging the bypass capacitors even further around is good. The design above from 00940 is clearly well on the way there, and one can imagine ages of carefull jostling of placement to get it as close to perfect as one might wish, but the combination of ideas is very much on track.

It is just annoying how tight things are around the IC, even just a tiny bit more room would have been so helpful. (Why did they have to put the useless test pins right at the end?)

 

[Clutz]

Quote:

Originally Posted by Francis_Vaughan 00940 seems to have beaten you to the punch a little, but yes, this is exactly the right approach. The idea of swinging the bypass capacitors even further around is good. The design above from 00940 is clearly well on the way there, and one can imagine ages of carefull jostling of placement to get it as close to perfect as one might wish, but the combination of ideas is very much on track. It is just annoying how tight things are around the IC, even just a tiny bit more room would have been so helpful. (Why did they have to put the useless test pins right at the end?)

Can't you use a larger PCB to address some of these problems? (I don't know anything about PCB layout- I'm just asking out of curiousity)