Very nice late-night-reading as always Rob
Can you tell us a little of the clock in the DAVE would be very intresting, and how you feel it stands against the other ultra high end DAC's with space age Cesium clocks (Rubicon) / Crystal Femto galaxy clocks ?
/Fredrik
The issue of clocks is actually very complex, way more of a problem then in simply installing femto clocks. People always want a simple answer to problems even if the problem is multi-dimensional and complex. I will give you a some examples of the complexities of this issue.
Some years back a femto clock became available, and I was very excited about using it as it had a third of the cycle to cycle jitter of the crystal oscillators we were using. So I plugged it in, and listened to it. Unexpectedly, it sounded brighter and harder - completely the opposite of all the times I have listened to lower jitter. When you lower jitter levels in the master clock, it sounds smoother and warmer and more natural.
So I did some careful measurements, and I could see some problems.
The noise floor was OK, the same as before, and all the usual measurements were the same. But you could see more fringing on the fundamental, and this was quite apparent. Now when you do a FFT of say a 1 kHz sine wave, in an ideal world you would see the tone at 1 kHz and each frequency bucket away the output would be the systems noise floor. That is, you get a sharp single line representing the tone. But with a real FFT, you get smearing of the tone, and this is due to the windowing function employed by the FFT and jitter problems within the ADC, so instead of a single line you get a number of lines with the edges tailing of into the noise. This is known as side lobes or fringing. Now one normally calibrates the FFT and the instrument so you know what the ideal should be. Now with a DAC that has low frequency jitter, you get more fringing. Now I have spent many years on jitter and eliminating the effects of it on sound quality, and I know that fringing is highly audible, as I have done many listening tests on it. What is curious, is that it sounds exactly like noise floor modulation - so reduce fringing is the same as reducing noise floor modulation - they both subjectively sound smoother and darker with less edge and hardness.
So a clock that had lower cycle to cycle jitter actually had much worse low frequency jitter, and it was the low frequency jitter that was causing the problem and this had serious sound quality consequences. So a simple headline statement of low jitter is meaningless. But actually the problem is very much more complex than this.
What is poorly understood is that DAC architectures can tolerate vastly different levels of master clock jitter, and this is way more important than the headline oscillator jitter number. I will give you a few examples:
1. DAC structure makes a big difference. I had a silicon chip design I was working on some years back. When you determine the jitter sensitivity you can specify this - so I get a number of incoming jitter, and a number for the OP THD and noise that is needed. So initially we were working with 4pS jitter, and 120dB THD and noise. No problem, the architecture met this requirement as you can create models to run simulations to show what the jitter will do - and you can run the model so only jitter is changed, nothing else. But then the requirements got changed to 15 pS jitter. Again, no problem, I simply redesigned the DAC and then achieved these numbers. So its easy to change the sensitivity by a factor of 4 just by design of the DAC itself - something that audio designers using chips can't do.
2. DAC type has a profound effect on performance. The most sensitive is regular DSD or PDM, where jitter is modulation dependent, and you get pattern noise from the noise shaper degrading the output noise, plus distortion from jitter. R2R DAC's are very sensitive as they create noise floor modulation from jitter proportionate to the rate of change of signal (plus other problems due to the slow speed of switching elements). I was very concerned about these issues, and its one reason I invented pulse array, as the benefit of pulse array is that the error from jitter is only a fixed noise (using random jitter source with no low frequency problems). Now a fixed noise is subjectively unimportant - it does not interfere with the brains ability to decode music. Its when errors are signal dependent that the problems of perception start, and with pulse array I only get a fixed noise - and I know this for a fact due to simulation and measurements.
3. The DAC degrades clock jitter. What is not appreciated is that master clock jitter is only the start of the problem. When a clock goes through logic elements, (buffers level shifters, clock trees gates and flip-flops plus problem of induced noise) every stage adds more jitter. As a rough rule of thumb a logic element adds 1 pS of more jitter. So a clock input of 1pS will degrade through the device to be effectively 4 pS once it has gone through these elements (this was the number from a device I worked on some years ago). So its the actual jitter on the DAC active elements that is important not the clock starting jitter.
The benefit I have with Pulse Array is that the jitter has no sound quality degrading consequences - unlike all other architectures - as it creates no distortion or noise floor modulation. Because the clock is very close to the active elements (only one logic level away), the jitter degradation is minimal and there are no skirting issues at all. This has been confirmed with simulation and measurement - its a fixed noise, and by eliminating the clock jitter (I have a special way of doing this) noise only improves by a negligible 0.5 dB (127 dB to 127.5 dB).
This is true of all pulse array DAC's even the simpler 4e ones. In short the jitter problem was solved many years ago, but I don't bleat on about it as its not an issue and because it's way too complex a subject to easily discuss.
I hope I have given a flavour here of some of the complexities.
Rob
