In I2S spec. there are three mandatory signals:
WCLK (word clock, or left right clock (LRCLK)) - 44.1k, 48k, 88.2k, etc.
BCLK (bit clock) - usually WCLK x 2 x 32 in most implementation
DATA (data) - include left and right channel data
MCLK (master clock) is optional, it is usually used to drive digital filter or to up-sampling the input signal.
What PCM1704 need is WCLK, BCLK, and DATA (only one channel). ["http://www.qlshifi.com/jszl/pcm1704.pdf"]
By setting NOS dsp in BYPASS mode, all dsp functions will be disabled (low pass filter, asynchronous clock, fifo) --- verified by Kingwa through email. WCLK and BCLK will pass through, DATA will be extracted and distributed to the corresponding PCM1704s. So the dac will operate in synchronous mode.
Although it is specified 768k in AGD's website. The actual measured PCM1704 input BCLK is (44.1k - 2.82MHz), (96k - 6.1MHz), (192k - 12.29MHz), (352k - 22.57HHz). So that means for 768k input the BCLK will be 49.152Mhz which PCM1704 can only support up to maximum 25Mhz. So I have strong reservation for the 768k spec.