Originally Posted by gerG Um, ok, I am confused again. I2S is multiplexed transmission of data, right?
gerG
I2S has 4 lines
Bit clock, that clocks in each bit one at a time (64fs)
LR clock, that says if the data is for the left or right channel and also dictates the word length for when all the data for that sample is entered in (1fs)
Master clock, that is the original rate of the of the cd players clock, usually 11.2896 MHz (256fs) or 16.9344 MHz (384fs) and is only really used for over sampling
And the Data line
The numbers in brackets are the speed at which these clocks go, relative to your original sampling rate frequency, for cd's is 44.1 kHz
You could say that I2S is multiplexed in that the left and right channel data is combined into the one data line, but that is it
Notice the SPDIF signal is "received" as a single stream (the multiplexed part of the discussion) then after reciver "lock" is separated back out into the individual I2S lines which are then sent along to the digital filter or if a Non-OS design the DA Converter chip itself.
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