The situation is more complex than it has a DPLL (digital phase lock loop) as all of my DAC's do indeed have a crystal oscillator at 104.25 MHz. I don't bang on about fS clocks and ultra low jitter for a number of reasons:
1. Its a very complex subject.
2. Pulse array DAC's are inherently jitter immune.
3. Use of fempto clocks would degrade sound quality as they employ PLL which although improve cycle to cycle jitter have poor low frequency performance and create low frequency skirts which are audible.
4. Source jitter is eliminated by the use of my DPLL - and we can see that on my plots of jitter showing zero jitter errors.
So what is so special about Pulse Array DAC's and jitter immunity? Well, conventional DAC's have a switching activity that is signal dependent - by that I mean it switches at a different frequency for different input data (DSD or delta-sigma), or it physically uses different switches for different data. This means that switching activity errors are signal dependent, and create signal correlated errors (distortion). The beauty of Pulse Array is that it always switches at exactly the same rate irrespective of input data; so this means the switching errors are constant, and become a DC error.
So what does jitter from the 104.25 MHz clock actually do? Well, I can see what it does by creating a simulation and adding random jitter - and when I do this with Pulse Array I get a fixed noise error. That is, random jitter creates a fixed noise completely independent of the data, so no distortion at all. Indeed, Pulse Array itself only creates a fixed noise error - no distortion - when one changes the tolerance of the Pulse Array elements (the resistor value). Actually, clock jitter and element mis-match is an identical error - you can't distinguish between element mis-match and clock jitter.
Now I now that the clock jitter for certain is insignificant because at the prototype stage I test for jitter and element mismatch error. And I do this by turning off the Pulse Array, so half the elements are permanently high, and half are forced low, so there is zero switching activity at all - in essence the DAC is off. And I know what the noise should be, as this is just from the analogue electronics and is mostly simply thermal resistor noise. Now I did this test at the prototype stage of Hugo 2, and found that one channel was perfect - the degradation was less than 0.5 dB when Pulse Array was on, but the other channel was degrading by 1 dB, which was unacceptable. It turned out to be a very subtle layout difference on one of the elements, and now this has been fixed in a later prototype and I get the usual less than 0.5 dB degradation when the DAC is turned on.
Now this 0.5 dB noise increase is insignificant, and it proves that the combination of master clock jitter and element mis-match problems has been solved; a better clock would have no bearing on performance at all, as this error is a fixed noise. Having said all this, one aspect that is very important is correlated jitter. So far I have been talking about random jitter, but as soon as we get jitter that is correlated, or signal dependent, then we are in massive trouble. Another benefit that Pulse Array has got is that the output flip-flops are only one buffer away from the crystal oscillator. And all of the components are discrete, with their own power; this means I can eliminate correlated jitter too. With chip based DAC's this is impossible to do, as internal noise will create correlated jitter inside the device as the clock is fed through the clock tree to the active elements. And I don't need to add, that a fempto clock with a PLL would have much bigger levels of correlated jitter.
I said at the beginning this was a complex subject...
Rob
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