[lazz]

HI guys. I have a Nad M51 and purchased a Singxer SU-1 on the way. I'm wondering about the switches that are talked about on the Singxer, what orientation would they need to be for the Nad. Thx.

 

[rb2013]

  I bought 2 modules, one modified to power the clean section, the other unmodified one power the F-1's dirty section (replace the USB +5V).
After testing I found no difference so decide to simplify the configuration and use my Dell computer USB power directly. The result comes at no surprise to me, since I already replace the ldo powering XMOS with a adp150 too from earlier mod. As to why last stage ldo's noise performance is more important than its feeding power, please refer to my other post - "http://www.head-fi.org/t/806397/audio-gd-new-nos-7-2016-edition-impression-thread/153" regarding to how to calculate output noise.
 
Picture of the unmodified module

 
Picture of modified one and the connection to F-1

 
The components are genuine, just the circuit board design and workmanship are terrible.
But since this is only a quick concept proving project, I will stick to my original plan to layout and build my own module in the future. I already have 5 LT3042s sitting on my desk for over one month.

Thanks for the pictures.  But I don't really see the benefit of these mods - if one is using a decent LPS and maybe some additional DC filtering (iFi DC iPur) and a W4S Recovery.
 
So this is my power chain, after AC line filtering - TeraDak DC-30W>iFi DC iPurifier>W4S Recovery>iFi iPurifier2>F-1
The noise is less then 1uv to the F-1, don't see how that can be made any lower.  Just the DC-30W and DC iPurifier takes the DC noise down to less the 5uv.
 
I use a modded JB that completely severs the PC USB +5VDC VBUS power - so absolutely no PC USB power can make it's way to the F-1, also use a 2G split USB - running only the data leg.

 

[bButcher]

  The noise is less then 1uv to the F-1, don't see how that can be made any lower.  Just the DC-30W and DC iPurifier takes the DC noise down to less the 5uv.

 
Every LDO have two important specs related to output noise: Output RMS Noise (Output Noise Spectral Density) & PSRR (Power Supply Rejection Ratio or Ripple Rejection); PSRR determines
how much noise will appear at its output due to noise from its input; Output RMS Noise specifies its own generated noise, usually the biggest noise source inside a LDO is its reference voltage circuit. So even you provide an ideal 0Vrms source to F-1, its on board 4 LDOs, 1 SMPS still will generate their respective rated noise.
 
On F-1's XMOS (dirty, before isolation) section:
    1.0V LDO - drive XMOS core; 85 ~ 90 mA
    3.3V LDO - dirve XMOS peripheral & isolation chips; 20 ~ 25 mA; generic LDO, usually noise spec. range from 50uVrms ~ several hundred uVrms
 
On F-1' CPLD/XO (clean, after isolation) section:
    3.3V LDO - drive XO; 14 mA --- ADP150: 9uVrms noise, PSRR > 60dB
    3.3V LDO - drive CPLD & isolation chips; 30mA; same generic LDO as on XMOS section.
    5V SMPS - drive the two LDOs; 75mVpp noise (100mVpp max)
 
So for an unmodified F-1 board, let's calculate the voltage noise feeding the femto XOs.
 
Assume the isolation is perfect, so 5V SMPS's PSRR approach infinity, and its total output noise will be sqrt[(75mV)^2 + (0 x Vn)^] =  75mVpp = 75/5.7 mVrms = 13.158 mVrms
And the output noise from ADP150 will be = sqrt[9^2 + (13158/1000)^2] = 15.94uVrms
 
So about 16uVrms is the best you can get for an unmodified F-1 irregarding to how good you power the F-1 externally. (vs. 9uVrms for SU-1, see reference)
 
After my first mod - the 5V SMPS replaced by battery and all 3.3V LDOs changed to ADP150s, the XO's feeding voltage noise is lowered to around 9Vrms.
 
Now the newest mod is try to further lower its noise to 1uVrms, and see what the impact it has sonics wise.
 
The following is a repost for reference:
 
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
First a little background about LDO's total output noise: a simple estimation is as followed,

------------------------------------------------------------------------------------------------------
Vout_total = sqrt[ Vout_n^2 + (Vin_n * PSRR)^2 ]
Vout_n:  LDO's output noise (9 uVrms @ 10Hz ~ 100kHz; ADP150)
Vin_n:    LDO's input source's noise
PSRR:   LDO's power supply rejection ratio or ripple rejection (55 ~ 70 dB @ 10Hz ~ 100kHz; ADP150)
 
(Note: only estimation, in practical integration over the whole bandwidth is required; also coupled noise from other sources must be taken into consideration too)
------------------------------------------------------------------------------------------------------
 
Take SU-1 as example: it use LM2940 as 5V LDO (54 ~ 72 dB @ 120Hz; output noise = 150 uVrms). Let say its input have 10 mVrms rippe/noise and assume LM2940's average PSRR ~= 60 dB or = 1/1000.
 
V5v_total = sqrt[ 150u^2 + (10m / 1000)^2 ] ~= 150.33 uVrms
Now look at 3.3V stage, let's also assume average PSRR ~= 60 dB (1/1000)
V3v3_total = sqrt[ 9u^2 + (150.33u / 1000)^2 ] ~= 9.0013 uVrms    ---- 5V from LM2940
V3v3_total = sqrt[ 9u^2 + (0u / 1000)^2 ] = 9 uVrms                      ---- ideal 5V source

Now you can see an only decent LM2940 (150 uVrms) will result to almost identical last stage noise level as a 0 uVrms ideal source. That's why Singxer choose LM2940 (more cost effective).
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

.. also use a 2G split USB - running only the data leg.

Thanks for the suggestion, it's on my to-do list; only I plan to build one myself.
 
Many thanks for your pointing to this wonderful device, so I can advance my whole setup to current state with minimal expense.

 

[rb2013]

   
Every LDO have two important specs related to output noise: Output RMS Noise (Output Noise Spectral Density) & PSRR (Power Supply Rejection Ratio or Ripple Rejection); PSRR determines
how much noise will appear at its output due to noise from its input; Output RMS Noise specifies its own generated noise, usually the biggest noise source inside a LDO is its reference voltage circuit. So even you provide an ideal 0Vrms source to F-1, its on board 4 LDOs, 1 SMPS still will generate their respective rated noise.
 
On F-1's XMOS (dirty, before isolation) section:
    1.0V LDO - drive XMOS core; 85 ~ 90 mA
    3.3V LDO - dirve XMOS peripheral & isolation chips; 20 ~ 25 mA; generic LDO, usually noise spec. range from 50uVrms ~ several hundred uVrms
 
On F-1' CPLD/XO (clean, after isolation) section:
    3.3V LDO - drive XO; 14 mA --- ADP150: 9uVrms noise, PSRR > 60dB
    3.3V LDO - drive CPLD & isolation chips; 30mA; same generic LDO as on XMOS section.
    5V SMPS - drive the two LDOs; 75mVpp noise (100mVpp max)
 
So for an unmodified F-1 board, let's calculate the voltage noise feeding the femto XOs.
 
Assume the isolation is perfect, so 5V SMPS's PSRR approach infinity, and its total output noise will be sqrt[(75mV)^2 + (0 x Vn)^] =  75mVpp = 75/5.7 mVrms = 13.158 mVrms
And the output noise from ADP150 will be = sqrt[9^2 + (13158/1000)^2] = 15.94uVrms
 
So about 16uVrms is the best you can get for an unmodified F-1 irregarding to how good you power the F-1 externally. (vs. 9uVrms for SU-1, see reference)
 
After my first mod - the 5V SMPS replaced by battery and all 3.3V LDOs changed to ADP150s, the XO's feeding voltage noise is lowered to around 9Vrms.
 
Now the newest mod is try to further lower its noise to 1uVrms, and see what the impact it has sonics wise.
 
The following is a repost for reference:
 
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
First a little background about LDO's total output noise: a simple estimation is as followed,

------------------------------------------------------------------------------------------------------
Vout_total = sqrt[ Vout_n^2 + (Vin_n * PSRR)^2 ]
Vout_n:  LDO's output noise (9 uVrms @ 10Hz ~ 100kHz; ADP150)
Vin_n:    LDO's input source's noise
PSRR:   LDO's power supply rejection ratio or ripple rejection (55 ~ 70 dB @ 10Hz ~ 100kHz; ADP150)
 
(Note: only estimation, in practical integration over the whole bandwidth is required; also coupled noise from other sources must be taken into consideration too)
------------------------------------------------------------------------------------------------------
 
Take SU-1 as example: it use LM2940 as 5V LDO (54 ~ 72 dB @ 120Hz; output noise = 150 uVrms). Let say its input have 10 mVrms rippe/noise and assume LM2940's average PSRR ~= 60 dB or = 1/1000.
 
V5v_total = sqrt[ 150u^2 + (10m / 1000)^2 ] ~= 150.33 uVrms
Now look at 3.3V stage, let's also assume average PSRR ~= 60 dB (1/1000)
V3v3_total = sqrt[ 9u^2 + (150.33u / 1000)^2 ] ~= 9.0013 uVrms    ---- 5V from LM2940
V3v3_total = sqrt[ 9u^2 + (0u / 1000)^2 ] = 9 uVrms                      ---- ideal 5V source

Now you can see an only decent LM2940 (150 uVrms) will result to almost identical last stage noise level as a 0 uVrms ideal source. That's why Singxer choose LM2940 (more cost effective).
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Thanks for the suggestion, it's on my to-do list; only I plan to build one myself.
 
Many thanks for your pointing to this wonderful device, so I can advance my whole setup to current state with minimal expense.

Great info - many thanks.  A knowledgeable poster like you adds much valuable information to this thread.  You shine a spotlight on some very interesting design elements.
 
I should add that I have done a bit to reduce AC line noise  - this is my AC chain: SR Teslaplex wall socket>Audience aRp1>Art Audio PB4X4Pro (separate ones for DDC, DAC and PC).  The aRp1 acts as an AC filter and balancer, the PB4X4PRO AC filter and isolation - using both common and differiant discrete designs.  They provide 40dB of AC line noise attenuation at high frequencies.
 
The LPS TeraDak DC-30W has been modded to replace the SU Pannie and gray generics with high PSRR Nichicon HW caps - then the DC output is further filtered by a iFi DC iPurifier (approx 316X to 100,00X noise reduction), this then feeds a W4S Recovery - with it's own ultra low noise (1uv) regulators, this is further filtered by a iFi iPur2 (1uv).  This is what feeds the F-1.  So I'm assuming that the noise coming into the F-1 is near zero.  The SU-1 has no option of providing a better DC power chain without mods.  So although it may have lower noise on a theortical level then the F-1, in a real world situation with high noise coming in, it may all add up to be the same in comparison to a well fed F-1.
 
So 16uv total noise with the stock components is not bad.  When I compared a DIYinHK Pro3a with it's 1uv LDO's and NDK SD clocks - I found the stock F-1 (without the uber power chain), better sounding.  I know some folks who have compared the new Pro3z, also with 1uv LDOs and have preferred the F-1.  In fact there is one for sale in the classifieds.
So noise at these low levels may not be a big factor in SQ.  Although I have to say with each gizmo I added to the F-1's power chain, it did make a difference in SQ, some minor some not as much.  Adding the LPS with Nichicon caps and the Recovery were probably the biggest, the iPur2 next, then the DC iPur.
 
A couple of questions though - what kind of noise does a Murata DA102 generate on the SPDIF vs the F-1's CPLD?  For you battery PS - many Li-ion battery have high noise, much higher then a well designed LPS, some expensive ones are lower.  Which battery are you using?  Have you measured it's noise?
 
Thanks again for the great info.
 
Cheers

 

[RickyV]

Every LDO have two important specs related to output noise: Output RMS Noise (Output Noise Spectral Density) & PSRR (Power Supply Rejection Ratio or Ripple Rejection); PSRR determines
how much noise will appear at its output due to noise from its input; Output RMS Noise specifies its own generated noise, usually the biggest noise source inside a LDO is its reference voltage circuit. So even you provide an ideal 0Vrms source to F-1, its on board 4 LDOs, 1 SMPS still will generate their respective rated noise.

On F-1's XMOS (dirty, before isolation) section:
    1.0V LDO - drive XMOS core; 85 ~ 90 mA
    3.3V LDO - dirve XMOS peripheral & isolation chips; 20 ~ 25 mA; generic LDO, usually noise spec. range from 50uVrms ~ several hundred uVrms

On F-1' CPLD/XO (clean, after isolation) section:
    3.3V LDO - drive XO; 14 mA --- ADP150: 9uVrms noise, PSRR > 60dB
    3.3V LDO - drive CPLD & isolation chips; 30mA; same generic LDO as on XMOS section.
    5V SMPS - drive the two LDOs; 75mVpp noise (100mVpp max)

So for an unmodified F-1 board, let's calculate the voltage noise feeding the femto XOs.

Assume the isolation is perfect, so 5V SMPS's PSRR approach infinity, and its total output noise will be sqrt[(75mV)^2 + (0 x Vn)^] =  75mVpp = 75/5.7 mVrms = 13.158 mVrms
And the output noise from ADP150 will be = sqrt[9^2 + (13158/1000)^2] = 15.94uVrms

So about 16uVrms is the best you can get for an unmodified F-1 irregarding to how good you power the F-1 externally. (vs. 9uVrms for SU-1, see reference)

After my first mod - the 5V SMPS replaced by battery and all 3.3V LDOs changed to ADP150s, the XO's feeding voltage noise is lowered to around 9Vrms.

Now the newest mod is try to further lower its noise to 1uVrms, and see what the impact it has sonics wise.

The following is a repost for reference:

<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
First a little background about LDO's total output noise: a simple estimation is as followed,


------------------------------------------------------------------------------------------------------

Vout_total = sqrt[ Vout_n^2 + (Vin_n * PSRR)^2 ]
Vout_n:  LDO's output noise (9 uVrms @ 10Hz ~ 100kHz; ADP150)

Vin_n:    LDO's input source's noise

PSRR:   LDO's power supply rejection ratio or ripple rejection (55 ~ 70 dB @ 10Hz ~ 100kHz; ADP150)

(Note: only estimation, in practical integration over the whole bandwidth is required; also coupled noise from other sources must be taken into consideration too)

------------------------------------------------------------------------------------------------------

Take SU-1 as example: it use LM2940 as 5V LDO (54 ~ 72 dB @ 120Hz; output noise = 150 uVrms). Let say its input have 10 mVrms rippe/noise and assume LM2940's average PSRR ~= 60 dB or = 1/1000.

V5v_total = sqrt[ 150u^2 + (10m / 1000)^2 ] ~= 150.33 uVrms
Now look at 3.3V stage, let's also assume average PSRR ~= 60 dB (1/1000)
V3v3_total = sqrt[ 9u^2 + (150.33u / 1000)^2 ] ~= 9.0013 uVrms    ---- 5V from LM2940

V3v3_total = sqrt[ 9u^2 + (0u / 1000)^2 ] = 9 uVrms                      ---- ideal 5V source


Now you can see an only decent LM2940 (150 uVrms) will result to almost identical last stage noise level as a 0 uVrms ideal source. That's why Singxer choose LM2940 (more cost effective).
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Thanks for the suggestion, it's on my to-do list; only I plan to build one myself.

Many thanks for your pointing to this wonderful device, so I can advance my whole setup to current state with minimal expense.

Hi bButcher,

Really great info, thanks a lot. I am following your lead, getting the last ldo this weekend. Any suggestion on the 1V LDO ? Driving the Xmos core sounds important enough. And where is that LDO hiding.

 

[bimmer100]

According to Leter @singxer he says they already are using adp150's for the clocks in the f1. And he says... And other Ldo's..
But he confirmed the clocks are definitely adp150 regulated.

 

[RickyV]

According to Leter @singxer he says they already are using adp150's for the clocks in the f1. And he says... And other Ldo's..
But he confirmed the clocks are definitely adp150 regulated.

And they are right, HA HA lol. Look at post 3436, from bButcher.

 

[bimmer100]

Ok, my mistake, I thought I read someone was actually removing the Ldo's and replacing them with adp150's. I wondered why.
Carry on with the DIY stuff.
Just wanted to mention if there was some confusion. I seem to be the one confused

 

[RickyV]

HA HA HA, and we are removing LDO's just not the clock ldo. We are repleasing the Xmos LDO on the dirty side and the cpld, iso chips LDO on clean side.

 

[RickyV]

Hi bButcher,

I am on a roll tonight. Are better capacitors before and after the LDO's an idea? Maybe parallel to the existing ones or repaceing them?

 

[lazz]

Just wondering , can The Icron Lan extender be connected to my pc by Rj45 then usb out to the Singxer SU-1.  And if so what it be any sound benefit as opposed to connecting the Singxer direct to pc via usb. Thx

 

[bButcher]

Originally Posted by rb2013 /img/forum/go_quote.gif
 
I should add that I have done a bit to reduce AC line noise  - this is my AC chain: SR Teslaplex wall socket>Audience aRp1>Art Audio PB4X4Pro (separate ones for DDC, DAC and PC).  The aRp1 acts as an AC filter and balancer, the PB4X4PRO AC filter and isolation - using both common and differiant discrete designs.  They provide 40dB of AC line noise attenuation at high frequencies.

Thanks for the information, AC power conditioning is my next focus considering I'm currently living in a big city, the line power just not in the premium condition.
 

So 16uv total noise with the stock components is not bad.  When I compared a DIYinHK Pro3a with it's 1uv LDO's and NDK SD clocks - I found the stock F-1 (without the uber power chain), better sounding.  I know some folks who have compared the new Pro3z, also with 1uv LDOs and have preferred the F-1.  In fact there is one for sale in the classifieds. So noise at these low levels may not be a big factor in SQ.  Although I have to say with each gizmo I added to the F-1's power chain, it did make a difference in SQ, some minor some not as much.  Adding the LPS with Nichicon caps and the Recovery were probably the biggest, the iPur2 next, then the DC iPur.
 
A couple of questions though - what kind of noise does a Murata DA102 generate on the SPDIF vs the F-1's CPLD?  For you battery PS - many Li-ion battery have high noise, much higher then a well designed LPS, some expensive ones are lower.  Which battery are you using?  Have you measured it's noise?

 
The previous analysis only focus on the voltage noise feeding to the XOs; On the other hand, XMOS's 3.3V power noise do affect its output I2S signals' jitter performance. If cpld's "Digital PLL" has limited correction capability, then the final result will somehow also depend on USB 5V's quality as you have experienced in your setup.
 
 
I don't own a Pro3a or Pro3z, so can only guess. Assume Pro3z follows XMOS's standard design, so Murata DA102 serves as isolation transformer to couple USB's D+, D- differential signals to XMOS, Pro3z also provide external DC in, so this two features together should provide the necessary blockage again all noise from computer's side. The problem is all components generate noise, even a humble resistor will generate thermal noise according to sqrt[4KBRT]. Not all components will put noise figures on their spec sheet, you can only measure it or estimate from their complexity and power consumption. In F-1, XMOS consume around 100mA, CPLD consume around 18mA; complexity wise one is uC one is only a cpld. So it is safe to say relatively XMOS generate a lot more noise than CPLD. This is the core concept of Singxer's design: to isolate noisy XMOS together with any noise coupled from computer from the femto clocks --- in any clock design voltage noise is the single biggest enemy; when XMOS's generated I2S signals pass through ISO7641, they will be further distorted; so the CPLD is there to restore I2S signal's jitter performance using the original femto clock signal. Compared to XMOS, Murata's generated noise can just be ignored; it will generate EM field, but I assume the board layout already consider this so no component or line is near enough to pickup the signal.
So the bottom line is: architecture wise I'll give the nod to Singxer; As to if XMOS 218, 1uV power, 6 layers circuit board will give Pro3Z any chance to fight back. I guess we can only judge after more comparisons are available.
 
I use sanyo (now panasonic) Li-ion 18650 batteries, I didn't measured them. From past experience common Li-ion battery has 1 order bigger noise performance than Sanyo's Eneloop AA battery.
eneloop's noise figure can be estimated from this paper: "Noise Measurements On Chemical Batteries" --- http://www.hoffmann-hochfrequenz.de/downloads/NoiseMeasurementsOnChemicalBatteries.pdf. From the figure, it's around 1 or 2 uVrms. So this will make my current 18650 battery's rms noise around 10~20uV. Not very good compared to state of art LDOs. But considering LT3042's PSRR > 80db @10 ~ 1M and LT1764's PSRR = 20~60db @10 ~ 1M, together at worst case still provide > 100db PSRR or 1/100000 scale factor. So 20uV/100000 = 0.2nVrms at LT3042's output, just disappear in the thin air.

 

[bButcher]

Really great info, thanks a lot. I am following your lead, getting the last ldo this weekend. Any suggestion on the 1V LDO ? Driving the Xmos core sounds important enough. And where is that LDO hiding.

1V is for internal computation, original LDO should be good enough. Noise spread out is via its peripheral pins which is powered by 3.3V LDO.
It's 6 pin component labeled "ADJG", the opposite side of the 3.3V LDO.

Are better capacitors before and after the LDO's an idea? Maybe parallel to the existing ones or repaceing them?

They should be 1uF cap as used for most 3.3V ldo, also suggested on ADP150's data sheet. If you are against ceramic cap for pizeo effect, you certainly can replace them with metal film ones, ex. Wima's. But I'm afraid the size will be too big to be nicely mounted on the boards. You can refer to data sheet's Application information, capacitor selection section for more detail. There are already 2x100uF cap on the input side (5V) and 1x100uF cap on cpld's 3.3V side, so you don't need to add any more caps. On XMOS's 3.3V front: Yes, additional output capacitor will help on "Load Transient Response", but in this case the load is relatively constant so it won't help much.

 

[motberg]

Would love to hear feedback on its combination with wyrd4s recovery which i am thinking of buying one. Tks

Hi, I now have 200+ hours on the SU-1 and just today removed the Recovery for a quick comparative listen.
My perspective, given this short comparative evaluation (Genesis Foxtrot, using JPlay mini in hibernate mode), is that the Recovery allows more separation of the elements within the sound-stage, removes some grain, and helps anchor the elements in their respective places.
This was not night and day however, for sure less than a 10% gain, but I think it would be a good upgrade to consider given the cost - (especially if you happen to have a suitable PS already available).
My recovery is powered by one of the better TeraDak LPS models with a ifi DC iPurifier using short PPA USB cables (following an Intona industrial).

 

[Miracle1980]

Does the Singxer-SU 1 reclock the usb signal coming from the pc?
I mean... Is it similar to what the Mutec is doing or it's just converting the signal?

Thanks