Rob, I'm trying to reconcile something I've read with what you've written here. First, let me caveat that my limited understanding of the relationship of DSD and PCM is based on various articles and YouTube videos, not based on experience working with the data itself (beyond listening to it!) -- primarily those of Andreas Koch.
Now,
Andreas has written that DSD (which I believe is just a Sony/Philips marketing name for
Delta-Sigma modulation, aka PDM) is the raw (digital) material from whence PCM is created. Thus, all PCM "begins life" as PDM/DSD:
If that's true, and that's the still the way it works... then I'm curious how timing errors in the DSD aren't also present in the resulting PCM.
- Is it perhaps a result of the decimation "collapsing" the errors into more accurate, neighboring samples? (I can easily see how this could be the case, but you'd still have a chance that you'd also be collapsing good timing into bad timing, no?)
- Is it some side-effect of the conversion from PDM to PCM?
- Is there more to the story that Andreas glossed over?
- Am I just not following what you guys are both saying? (totally possible...)
Please note I'm outside my depth on all of this and I have mad respect for you and the work you're doing. I'm just trying to fit all these conceptual puzzle pieces together!
Thanks so much!
No worries - we are dealing with a complex situation. Moreover, absolutely nobody talks about the issue of timing errors with respect to amplitude on a DAC or ADC, so if the professionals that spend their life working on this and don't see the issue, then enthusiasts have no chance!
Firstly, let's clear up a few things. Delta-sigma modulation, which all modern ADCs rely on, are two types - n-bit, and one bit or DSD. No high performance ADC uses 1 bit - they are all n-bit, typically 5 bits. And this is because of fundamental limitations of 1 bit modulation.
A delta-sigma ADC takes an analogue input (and for this discussion this can have the value between -1 and +1) and via the quantizer will truncate the value. A simple n bit modulator will say have 5 levels - +2,+1,0,-1,-2. A 1 bit modulator will have -1 and +1 as the only output. The input will of course be different to the quantised output, and a subtractor is used to compare the analogue input to the quantized output. The output from the subtractor is fed into a noise shaper, which is a set of integrators, amplifying the error. This amplified error is then added to the input signal, and is fed to the quantizer.
Let's say the input is now 0. With DSD, the output will be (say) +1. The subtractor will then be (input - output) or 0 - +1 or -1. This is then fed to the noise shaper, and the output will tend to go negative - then the next output from the quantizer will be -1. This in turn creates an error, and the modulator goes thru a sequence of +1,-1+1,-1... in order to create the input of 0. Everything is fine, the modulator is stable. But what happens when the input gets higher say +1? Then the output is fixed at +1, and the noise shaper will demand greater than +1 - but it can't. So then the integrators clip or saturate, and all hell breaks loose - it goes unstable. So to minimise this, the input is limited to + or -0.5; but the modulator will still want to use +2 as a overhead value, and it can't have this, and so the modulators gain is being curtailed. This creates modulator noise floor modulation, and it is inescapable.
But an n bit modulator will always have headroom - so when +1 is the input, then +2 is allowed, and the modulator will choose +2,+1 or 0 as its next value - so the modulator state is signal invariant - that means the modulator gain or stability does not vary with input signal, and so will not suffer from modulator induced noise floor modulation (it will suffer from other forms of noise floor modulation but that's another story). Because an N bit modulator has headroom, then we can use dither to linearise the quantizer.
But we aren't yet talking about the timing issue. So with DSD, if the signal goes from 0 to +1, then the OP will go to +1 immediately. So no OP delay. If it goes from 0 to +0.001, then there will be a delay, and the time it takes to respond will depend upon the gain of the modulator - which principally depends upon the rate of oversampling and the design of the noise shaper.
Now with an N bit modulator we can dither the input to the quantizer, and this can reduce the transient timing with amplitude error dramatically, as the timing error brecomes random - sometimes too early, sometimes too late, which is fine. 1 bit DSD is impossible to dither correctly, as the modulator will go unstable.
Clearly, the faster the modulator works, the better it behaves; also how effective the dithering also improves the issue; with pulse array I can eliminate the issue entirely, with the appropriate order of noise shapers (that is number of integrators - it's one reason why I have huge levels of noise shaping), the design of the modulators, and the appropriate setting of the number of elements (the value of N for an N bit modulator) and the oversampling rate (another reason why I run at 30 times faster than conventional noise shapers).
The davina project ADC will not suffer from this issue (completely impossible with DSD), nor will it have any measurable noise floor modulation (impossible with any current ADC), with together with the elimination of aliasing from decimation, will make it rather unusual...
