| Originally Posted by shimage Out of curiosity, why does it need to be leaded? |
| Originally Posted by dsavitsk Because the cap it is replacing has leads. |
| Originally Posted by Filburt How do I find 6k resistors? I managed to find 1.2k, but all I can find is 6.04k. |
| Originally Posted by jbloudg20 6.04K will work fine. |
| Originally Posted by Filburt Okay, so do I use a 1k resistor over the C1L/R slots and jumper R2, or do I jumper those slots and use the 1k in the R2? Morsel suggests using 1k in C1, but something has to be done about R2, right? |
| Originally Posted by amb Put 1KΩ through-hole resistors in the C1 positions. R2 stays unchanged -- 100KΩ. Don't jumper it or you'd have short circuited the input to ground. See the schematic! |
| Originally Posted by shimage So, uh, since I've already asked one dumb question, I thought I'd ask another. Why is it that you can neglect the pot when you put a 1k resistor in "C1", but not if you jumper it? I ask because amb and morsel seem to ignore the pot when choosing R3/R4, but Tangent explicitly states that C1 (when it's a capacitor) blocks pot so you don't have to worry about it (and its variable resistance). What am I missing here? |
| Originally Posted by amb That's not a dumb question. It's good that you asked. When C1 is in place, you ignore the pot and only use R2 for the purpose of calculations, because C1 blocks DC as "seen" by the opamp input, so R2 is the only DC path. When C1 is removed, then things become a lot more complex. The DC path becomes R2 || (R1 + effective pot resistance). However the effective pot resistance is not simply its 10KΩ value. At minimum volume position the efective pot resistance is 0Ω because its wiper is shorted to ground. This is where we can ignore the pot. On the other hand, the effective pot resistance would be 10KΩ if it's turned to maximum position and there is no source connected (or if the output stage of the source has an output coupling cap without a drain resistor going to ground, thus blocking DC). This would be the worst case scenario where the R2 || (R1 + effective pot resistance) would be 9.9KΩ (for a 10KΩ pot, and R1 = 1KΩ and R2 = 100KΩ). This is unbalanced from that of the inverting side (R3 || R4) of 1KΩ if you use R4 = 6KΩ and R3 = 1KΩ. In the case of a source with direct-coupled output (no output coupling caps) and low output impedance, then at maximum volume position the effective pot resistance is also in parallel with the output impedance of the source, which then becomes near 0 and can be ignored (similar to the case where the pot is turned to minimum). In this scenario, at the half-way rotation of the pot (not mechanically half-way, but resistively, because this is a log taper pot), the effective pot resistance is one half of the real pot value because the 10KΩ is divided in two, and effectively in parallel. As you can see, things get complicated because of the pot, and when C1 is removed and replaced with a resistor, the output DC offset will vary according to the pot's position. Fortunately, due to the low resistor values involved, the voltage developed on each input of the opamp due to the combined resistances are low, so the imbalance when the pot is turned up does not cause a huge DC offset problem. It is for this reason (and for simplicity's sake) we ignore the effect of the pot. If you use high resistor values, on the other hand, even a small imbalance between the two sides can lead to a very large DC offset problem. Take our low resistor values as an example (pot = 10KΩ, R1 = 1KΩ, R2 - 100KΩ, R3 = 1.2KΩ and R4 = 6KΩ): At minimum pot position the two sides are basically balanced so the DC offset contributed by the opamp input bias current is essentially 0. At max volume position and no source (worse case) the + side combined resistance is 9.9KΩ and the - side is 1KΩ. The AD8397's input bias current is 1.3µA typical. So the voltage developed by this current is about 13mV at the + input and 1.3mV at the - input. The difference between the two voltages multiplied by the voltage gain of the amp yields a maximum output offset of 69mV. Not too good, but keep in mind that this is for the max volume scenario with a disconnected source. Also, having experimented with a fairly good sample of AD8397s I found that they tend to have slightly negative DC offset when the resistances are truly balanced, so the increase toward positive is cancelled somewhat by this tendency. For what it's worth, I measured our Mini³-fied PINT and found that the DC offset (min volume, max volume) was (-6.6mV, -2.6mV) and (-9.2mV, -6.6mV), respectively for the two channels. So much for the calculations, the reality is much, much better. I think part of the reason may be found in the input resistance spec of the AD8397. It's specified to be 87KΩ, which, if we're going to account for that, should be made to be in parallel with the combined resistance at each input as well, and this reduces the effective resistor values even further. Accounting for the input resistance in our calculation drops our worse-case DC offset above down to 61mV. It still doesn't reflect the measured reality, but oh well. Nevertheless, the calculations are worthwhile as a reference. Accounting for the 87KΩ opamp input resistance, let's look at an example where high resistor values make things really bad. Assume that we have replaced C1 with 1KΩ and R2 = 100KΩ, but R3 = 120KΩ and R4 = 620KΩ. At maximum volume the combined resistance is 8.9KΩ at the + input and 46.6KΩ at the - input, and we get ~294mV of offset (
Just as a footnote, the above calculations assume that the DC offset is only due to the opamp's input bias current. In reality there are other factors that influence the actual offset (such as the matching of the internal transistors, etc.). However with these bipolar opamps, the input bias current is relatively high and are thus dominant. No so with FET input opamps -- The resistances can be very mismatched at the two inputs with little effect. Long-winded post -- but I hope this sheds some light on the subject. Edit: added actual measurement data. |
| Originally Posted by Filburt Why is it that, when adding C1 in, we up the resistor values so much? |
| Originally Posted by nysulli so then the proper method of changing the gain would be to leave R3 at 1k and change R4? say dropping the gain to 4 we'd leave R1 at 1k, R2 at 100k, R3 at 1k, and R4 at 3k, is this right? |
