New Audio-gd R-7, R-7HE R-8, R-27, R-27HE, R-28 Flagship Resistor Ladder DACs and DAC/amps
Oct 20, 2021 at 10:15 AM Post #7,862 of 11,282
The Amanero/Xilinx/Altera changes alter the sound and takes some time to get used to the new presentation. On the R7HE mk2 initially sounds more laid back. But after some listening there is less grain and sound is more refined (less raw). Brass has less bite, bass good, vocals excellent. And no more pops when using the Linux server! Excellent! Takes a few days to get accustomed to the new sound so be patient.

I initially loaded the files onto the HE7 mk2. Drastically changes the sound of that DAC. So will back out of the changes and start again with the knowledge gained. The HE7 is in the middle of break in period.

Kingwa says the new firmware tightens the external clock PLL for better precision of the synthesized clocks. This DAC PLL change is the same as the DI20 on firmware version 3.9x and above.
 
Oct 20, 2021 at 4:15 PM Post #7,863 of 11,282
Ask Kingwa. You may have the latest and greatest already.

The amanero is not mandatory, although i figure Kingwa tuned the sound using it.

To flash the fpga fw,, the _pll_ version i mean, your need to have one of the xilinx cpld chip inside the dac updated with a new fw too. This is mentioned in the zip file.

For that purpose, you need the Xilinx Impact programming sw (Windows program). And a usb device to make the programming (see the previous post by DacLadder for a picture) . This is quite a pain to setup, even more so than for the fpga.

For those doing the updates, give it some time. There is some burn-in occuring, it seems. The sound will lack meat in the first 15-20 hours. But the soundstaging and imaging make a significant step fwd.
Hi Fred
Do you have the link for the USB needed to flash the PLL program?

I will get my HE-7 next week, but I would like to buy now this USB device because if I need to buy it abroad, it will take two to three months to get here.

On the other hand, wich device is used for flashing the Amanero firmware upgrade? The USB blaster?
 
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Oct 20, 2021 at 4:28 PM Post #7,864 of 11,282
Hi Fred
Do you have the link for the USB needed to flash the PLL program?

I will get my HE-7 next week, but I would like to buy now this USB device because if I need to buy it abroad, it will take two to three months to get here.

On the other hand, wich device is used for flashing the Amanero firmware upgrade? The USB blaster?
Not sure which Xilinx programmer works these days, I have an old one from 2018, made in China. Model DLC9LD.

The Amanero update just require the sw and a usb cable.
 
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Oct 21, 2021 at 8:05 AM Post #7,866 of 11,282
Is it PLL for external clock version now, not a clock synthesizer?
It's what Kingwa calls the clock circuit.

From Kingwa...
"When the Di20HE released it built in the same external digital PLL as the R7 models.
Later when the DI20HE released the 3.9 firmware that is apply the new external digital PLL design .
Now the R7 models apply the same PLL design as the DI20HE."
 
Oct 21, 2021 at 9:08 AM Post #7,867 of 11,282
From Kingwa...
"When the Di20HE released it built in the same external digital PLL as the R7 models.
Later when the DI20HE released the 3.9 firmware that is apply the new external digital PLL design .
Now the R7 models apply the same PLL design as the DI20HE."
It makes sense. Confusion was caused by mention in some posts of a clock synthesizer without PLL. Digital PLL gives at the moment performance level comparable to the best crystal oscilators.

A word 'external' use probably means that a digital PLL is implemented in a dedicated FPGA, but not sure. It could also mean a licensed third-party commercial solution.
 
Oct 21, 2021 at 9:23 AM Post #7,868 of 11,282
The new firmwares are sounding great with the HE7 mk2 as well. OS 8x no less. It is like a small burn in is needed to get to best sound. And also readjust the brain with the differences in sound.

And using internal USB. It sounds really close to the DI20HE over I2S.

I will ask Kingwa what is the schedule for 2020 and 2021 firmware...
 
Oct 21, 2021 at 9:24 AM Post #7,869 of 11,282
Hi guys
I will get my HE-7 next week and I will burn it before changing firmware.

Nevertheless, I would like to understand a little bit about this new firmware option.

As I understand, the new FPGA and CPDL firmwares are supposed to be better when using external master clock. AM I correct?

On the other hand, this is Kingwa's answer for Amanero firmware:

"The default Amanero firmware is best for the Windows and mac version .
It is not the latest version , but it better than the latest version in the Windows and Mac.
If you don't running it in the Linux , don't need update it."
 
Oct 21, 2021 at 9:44 AM Post #7,870 of 11,282
As I understand, the new FPGA and CPDL firmwares are supposed to be better when using external master clock. AM I correct?
That's what is implied. But there are Linux optimizations as well in the PLL_N firmware. And no telling what else. You just have to try them to see for yourself. Some users may not like the newest f/w. Understandable...
 
Oct 21, 2021 at 10:45 AM Post #7,872 of 11,282
When loading only the PLL_N Xilinx and Altera the sound became darker and more laid back with the default Amanero. The sound balance and highs were restored when the Linunx optimized Amanero code was loaded afterward. Doesn't make much sense why the Amanero has such great affect but happened on two Mk2 DACs.

PLL_N with external clock provides less grain, better imaging, and outstanding bass. Takes a while to adjust expectations and differences.
 
Oct 21, 2021 at 6:26 PM Post #7,873 of 11,282
It makes sense. Confusion was caused by mention in some posts of a clock synthesizer without PLL. Digital PLL gives at the moment performance level comparable to the best crystal oscilators.

A word 'external' use probably means that a digital PLL is implemented in a dedicated FPGA, but not sure. It could also mean a licensed third-party commercial solution.
It's implied without hw pll. Cause they do not have required level of performance to manage the 10M input properly, at least what is available on the fpga is not.
 

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