LT1028 in a PPA

[thrice]

I'm trying out the LT 1028 in my PPA (w/Larroco Diamond Buffer) and I am having some problems.

Conditions:

R3=1K; R4=4.32K Gain of ~5.
Biased to Class A at 1.5mA
DB Bias voltages set to 50mV
LT1028CN8 in left and right opamp sockets and opa627 in ground socket.
STEPS power supply at 24V.

The offset voltages are what concern me. With the LT1028 I get the following:


IG to OG 0mV
IG to OL 7.5mV
IG to OR 3.XmV

Same measures between pins 6 on the DB unit.

However, the DC offset varied dramatically when I turned the volume pot...at the highest volume it reached 12mV in the Left channel and 9mV in the right.

Is this OK?

These offset reading are pretty high compared to the OPA627/637s I've tried. With a pair of Grado SR60s I get a very loud pop when I turn the amp off and on...I didn't try it with my HD600s!

How can I adjust the offset of an opamp? Would raising the gain to 11 help (R4=10K)?

PS. I also tried the LT1028ACN8 but those gave me DC offset voltages of 25mV in each channel.

 

[ppl]

the Lt1028 has high offset because it has a Bipolar input stage if it was not for the imput Bias current cancilation on the Lt1028 it would be like all other Bipolar input opamps and have a DC offset change by severial volts with volume control posistion.
The PPA is designed for FET input opamps with a bandwidth of 30 MHz or less anything elce may or may not work

 

[jnewman]

The easiest (but not necessarily best from a sonic perspective) way to fix that is to add output caps. Most people hate caps in the signal path, but they'll get rid of the DC offset with bipolar op-amps. Seems people recommend something like a 100uF and a 1uF in parallel on each signal out.

 

[peranders]

I think LT1028 is best suited for high gain low noise applications, together with low impedance signal sources also.

If you want this opamp you must have control over the input bias currents and also have a goal of how much output offset voltage you can tolerate. Just replacing without carefully examine the properties of the opamp is (or may be) dangerous. Better isn't always better.

 

[guzzler]

Personally, I don't think those offset values are much to worry about for High-Z phones like your HD600s. I've got AD797s in my PPA and the offset IIRC is around the 15mV range, so I'm don't use bass boost but that's not an unreasonable figure, and certainly doesn't appear to be harming the phones and the AD797s sound lovely to boot. They're bipolar fast amps, btw

g

 

[thrice]

Thanks for all the answers/advice. i don't think I want to go the input cap route.

It seems like raising the gain to 11 might help? Unfortunately I don't know enough about electronics now to fully understand some of the aforementioned answers. I just want to roll a few opamps in the PPA and experiment.


Quote:

Originally Posted by peranders If you want this opamp you must have control over the input bias currents and also have a goal of how much output offset voltage you can tolerate.

Ok, how do I gain control over the input bias currents? I'd like to minimize the DC offset to be below 1mV.

I was looking at the datasheet and saw a section talking about Offset Voltage Adjustment. It looks like if I tie pin 1 to pin 8 with a 1K ohm resister and then tie that to the voltage going into pin 7 I can minimize the DC offset. Does that make sense?

Thanks in advance.

 

[tangent]

Quote:

I don't know enough about electronics

Not to pick on you, but isn't this precisely the problem? There's only so far you can go if you don't know what you're doing.

Quote:

how do I gain control over the input bias currents?

They're an inherent part of the chip design. You don't control them, you cope with them. With FET-input chips, they're so small that you can ignore them. With bipolar-input chips, these currents force enough voltage across the feedback resistors that they're significant.

By fiddling with the feedback resistors' values, you can change these voltages. The simple case is with a CMoy type design, which I talk about in this article. But that doesn't fully apply to the Jung multiloop case.

 

[BrokenEnglish]

/deleted by myself: sorry... off-topic

 

[ppl]

the 7 mV in the ground Ch indicates the 1228 is probaly oscilating and you should reduce the sise of the 100 pF cap in the Gd ch to about 33uf the LT1028 should produce 0 Mv offset in the ground ch and any op amp in that posistion should do the same or ditch it its unstable

If you read the data sheet the LT1028 is not normaly unity gain stable

 

[markr1957]

If you must have gain less than 10 I suggest you try the LT1128 (has lower slew rate but more than fast enough for audio). This has equally low input noise voltage but it is unity gain stable in non-inverting mode. The LT1028 is only (barely) unity gain stable in inverting mode operation.
Both the LT1028 and LT1128 have output offset adjustment pins. Put a (1K or greater) trimpot between pins 1 and 8, and tie the pot wiper to the positive supply (pin 7). The usual cause of output offset is unequal input resistance on pins 2 and 3 to ground, causing unequal input offset currents, so the difference is amplified and presented at the output as an offset voltage. To minimize input offsets the resistance to ground from pin 2 (source resistance plus circuit series resistor) must be equal to the resistance from pin 3 to ground - if you tie pin 3 directly to ground you will never get rid of the offset (for inverting amplifier circuit). If your circuit is non-inverting you get the same problem if you tie pin 2 to ground.

 

[Avro_Arrow]

Why are you replying to something that was posted six years ago..?

 
Quote:

If you must have gain less than 10 I suggest you try the LT1128 (has lower slew rate but more than fast enough for audio). This has equally low input noise voltage but it is unity gain stable in non-inverting mode. The LT1028 is only (barely) unity gain stable in inverting mode operation.
Both the LT1028 and LT1128 have output offset adjustment pins. Put a (1K or greater) trimpot between pins 1 and 8, and tie the pot wiper to the positive supply (pin 7). The usual cause of output offset is unequal input resistance on pins 2 and 3 to ground, causing unequal input offset currents, so the difference is amplified and presented at the output as an offset voltage. To minimize input offsets the resistance to ground from pin 2 (source resistance plus circuit series resistor) must be equal to the resistance from pin 3 to ground - if you tie pin 3 directly to ground you will never get rid of the offset (for inverting amplifier circuit). If your circuit is non-inverting you get the same problem if you tie pin 2 to ground.

 

[FallenAngel]

That is absolutely an UBER 1st post!