Quote:
Originally Posted by gregorio /img/forum/go_quote.gif
Thanks for the info Dan, very interesting. I brings up a question though, from a mastering standpoint. If I were to apply noise shaped dither, as part of the mastering process when reducing a 24bit master to a 16bit distribution version, and I use a distribution algortihm, which redistributes the vast majority of the quantisation distortion (noise) to the high frequency band, is it possible this additional HF energy could negatively impact the jitter in a DAC? Would this be worse in an oversampling (delta-sigma) DAC or is the amount of additional energy we are talking about, (probably 3 or so LSBs worth at a guess) insignificant?
Cheers, G
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I would say no and no.
As I mentioned in the earlier post, jitter has little impact on signals of very low frequency and amplitude. It has more impact on signals with high frequency and amplitude. Let me state it a little clearer - signals with BOTH high frequency and amplitude. A high slew rate (fast changing slope of voltage over time) calls for BOTH high amplitude and high frequency.
Say your signal is a 20KHz sine wave, and it is 10V peak (20V peak to peak). Then the maximum slop is around the zero crossing, and it is 1.256V per microsecond. If your jitter is late by sat 1nsec, the error is 1.256mV (milivolts). That is a lot! It costs you 4 LSB's error on a 16 bit recording. It costs you 64 LSB's on a 20 bit...
Say your signal is a 20KHz sine wave, and it is .1V peak (.2V peak to peak). The slew rate is 12.56 milivolts. It costs you .04 LSB's error on a 16 bit recording. It costs you .64 LSB's on a 20 bit...
Say the signal is 10V amplitude but the frequency is 200Hz. Again, the slew rate is 12.56 milivolts. It costs you .04 LSB's error on a 16 bit recording. It costs you .64 LSB's on a 20 bit...
Noise shaping dither:
Dither, even a noise shaping dither, is only a very small amplitude signal. It may be higher at around 20KHz, but it is still only a few LSB's so the slew rate contribution due to noise shaping dither is very small.
Oversampling DAC:
Oversampling does not alter the slew rate of a signal. It only adds intermediate sample values, but the slop of the signal is the same. Say you have a slop that is 1V per usec, and say you sample every usec. The first sample is at 0V, the second sample is at 1V, the third sample is at 2V... The slope between the first and second samples is clearly 1V per usec. If we up sample by X2, we leave the original samples as they are, but we insert additional samples every 1/2 usec. So now the first sample is at 0V, the second is .5V at 1/2 usec, the third is still at 1V at 1usec... The slope stays the same. If you up sample by say X4, both the change in voltage and the time between samples (on the slope) is halved again, so the slope is still the same.
Up sampling “fills in” more “dots” but the signal envelope is the same. The final analog filter removes the “steps”, making for a smooth slop. The analog filter has an easier life filtering many small steps (compared to few large steps), and that is the main advantage of up sampling, (contrary to much marketing hype such as "more bits").
So the jitter is not going to harm the signal due to up sampling. At least not in principle (no conceptually). If you observe such a thing, I would look for another implementation specific reason.
And also worth noting, a multi-bit sigma delta is less jitter sensitive then the older 1 bit sigma delta (as in DSD which is the engine of "supper audio CD" format). A 5 bit multi-bit modulator is less jitter sensitive then say a 3 bit. I am not advocating a 5 bit over a 3 bit, it is just one of the very many considerations.
Regards
Dan Lavry
Lavry Engineering