@Tom-s sure no problem! Although, the specific implementation in this amp might not be so useful as it uses local negative feedback, which mitigates some of the bandwidth issues and also lowers the peak output voltage. But talking through the design might help.
Here is the general schematic for this amp.
As you can see, the H63 stage uses a low current CCS load, IXTP08N100D2 and LND150 in cascode. The feedback loop / the H63 cathode are buffered by a FQD3P50 PMOS (got that idea from SpreadSpectrum on diyAudio). There is some cathode bias provided across the PMOS / 620ohm feedback resistor, around 6V. But to properly bias, 3x AAA batteries are placed at the grid, putting it at 4.5V, so the grid-to-cathode bias is in the -1.5 to -2V range for proper biasing. So it is a mixed bias scheme, fixed and cathode combined. Given the grid bias, there is a 0.22uF capacitor between the volume pot and the H63 grid. The H63 stage works into a parallel 6BX7 cathode follower buffer, which is then direct-coupled to the 801A grid. The 801A is A2 biased, so positive grid current is given by the cathode follower. Local feedback is taken from the 801A plate to the H63 cathode, again buffered by a PMOS. There are no capacitors in the feedback loop (I tested this audibly and the sound was so much worse with a cap), so there is DC in the loop as well and the voltage drop across the 620ohm feedback resistor contributes to the 6V bias at the cathode of the H63. The high gain of the H63 is utilized for the feedback loop, so the closed loop voltage gain of the H63 stage is only about 22.
As I am writing this out, I can't believe I made this amp. It's crazy, but it works.
I took some repeat measurements this morning. Distortion at 1W into 8ohms is 0.3%. It does 7W at 1% THD. Here is the frequency response.
I assume you would probably be doing a more conventional common cathode gain stage. In that case you really just have to worry about the Cmiller and the capacitance the tube is driving.
Cmiller for the H63 is somwhere in the 200-240pF range, so resistance from the grid to ground is something to pay attention to. Using a 50K pot, maximum resistance from grid to ground would be around 12.5K. Assuming a Cmiller of 240pF and using f = 1/(2*pi*R*C) = 1/(6.28*12,500ohms*(240*10^-12 farads)) = f-3dB of 53kHz. So probably would not want to go higher than a 50K pot. Since we've been talking about AVCs, which have a lower source resistance than a conventional pot, that would be another option to mitigate the high Cmiller of the H63.
In terms of the load and the capacitance it will be driving, using a low capacitance CCS NMOS like the IXTP08N100D2 would be a good approach. If you don't want the H63 to work into a buffer stage, like in my amplifier, you could take the mu output of the CCS, which would lower the output impedance substantially, and have it work directly into an output stage. Only thing to keep in mind here is the B+ at the top of the CCS has to cover the peak voltage swing of the H63 plus the dropout voltage of the CCS. In terms of the cathode, trying a bypassed vs unbypassed cathode resistor would probably have to be experimented with, it's possible an unbypassed cathode resistor might hurt the bandwidth. Bias current is too low for an LED in the cathode. The other option would be to ground the cathode and used battery bias. A single AA at 1.6V would get the job done, but of course you would need something to block DC at the grid, either an input transformer with the AA between the secondary and ground, or a capacitor.
..... ... *(Yes, probably will do that since I've been collecting H63's just for this purpose; it's the amplification that makes it so interesting). It's been on my to use list for years now.
the amplifier has some nice kick. Been four weeks since I ordered my B215, then I can record anything I want...halfway there.
