Regus
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- Oct 30, 2004
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I have been designing an oversampling DAC for the past year, year and a half (in my rare spare time) and I have been thinking about input and DAC clock variances...
I mean if the speed of the input clock is off even by 1% we are talking 441 error samples a second in a simple 44.1kHz scenario...
Now a TENT XO clock is specified for +/- 50ppm that would be 0.005% now if we asume both ends of the system uses something like this we are talking a maximum variance of 0.01% which is still 4 error samples per second... now while this might qualify as acceptable it is asuming both clocks are TENT XO clocks or equivalent...
Now I was wondering is it possible to design a low jitter clock the speed of which can be electrically addjusted to within say 500 ppm of the target frequency in 10ppm steps or better.
With such a clock it would be possible to compare input and DAC frequency and adjust the latter to match the input without having to fight with input jitter throughout the whole system...
Or is the some brilliantly simple solution I have overlooked?
I mean if the speed of the input clock is off even by 1% we are talking 441 error samples a second in a simple 44.1kHz scenario...
Now a TENT XO clock is specified for +/- 50ppm that would be 0.005% now if we asume both ends of the system uses something like this we are talking a maximum variance of 0.01% which is still 4 error samples per second... now while this might qualify as acceptable it is asuming both clocks are TENT XO clocks or equivalent...
Now I was wondering is it possible to design a low jitter clock the speed of which can be electrically addjusted to within say 500 ppm of the target frequency in 10ppm steps or better.
With such a clock it would be possible to compare input and DAC frequency and adjust the latter to match the input without having to fight with input jitter throughout the whole system...
Or is the some brilliantly simple solution I have overlooked?