[Nerull]

I've finished on of the many DAC I2S boards I'm going to make.
It's for the PCM1794. No output stage was put in, because I want to be able to swap them out for testing.
Attached is the schematic and the board.
Any input would be greatly appreciated!

~Tom

 

[flecom]

I was actually designing the EXACT same thing for a cd player im working on...

what is the TPS3125 doing?

if you do decide to prototype some let me know i need a pair of them...

 

[Alf]

Quote:

Originally Posted by Nerull I've finished on of the many DAC I2S boards I'm going to make. It's for the PCM1794. No output stage was put in, because I want to be able to swap them out for testing. Attached is the schematic and the board. Any input would be greatly appreciated! ~Tom

A few suggestions. Bring the ground plane to the top. Put as many traces to the bottom as possible. Add 100nF capacitors as per schematic in the datasheet.

 

[JahJahBinks]

Quote:

Originally Posted by Alf Bring the ground plane to the top. Put as many traces to the bottom as possible.

Why don't you want to surround traces with the ground plane?

 

[guzzler]

The ground plane is only effective when it is above the trace, as you can imagine the current loop being in 3D as it were. With only one chip, you're also forced to use vias for grounding. This is preferred in multichip systems as it allows ground protected traces between ICs, but is needless in a single chip system. Direct connection is better for the grounding as you're not invoking vias which have an associated inductance which modules ground sympathetically with the signal

 

[JahJahBinks]

I see what you are saying. I was thinking that you already have a ground plane and you add another ground plane on the signal layer to reduce noise pickup (sort of like a guard ring)

 

[Garbz]

The schematic looks like a good implimentation. I just have to say something about the interconnection.

The DAC is current output and a very small current at that. You'll want to keep the cable going from your DAC to the output stage as small as physically possible.

The I2S input has a different problem. Using straight out wires here will radiate RF which may or may not be a problem. One partial improvment could be to use a 8 pin DIL headder instead of a 4 pin SIP. Every second strand connected to ground. This would give a similar setup to the ATA-66 standard for HDDs, where an 80 pin cable is used for 40 electrical connections with every other cable grounded to reduce interference.

 

[Nerull]

Okay, so I'll use the ground plane on the top (I suppose it'll save on costs as well) to limit vias going to ground (due to inductance). I'll also take Garbz advice on using a 8 pin DIL header rather than the 4 pin SIP.

The TPS3125 is used to pull the PCM1794 out of reset; otherwise it will not work. It's to tell the DAC that the voltage is stable and to turn on all the stuff in it.

And sure Flecom, as soon as my design is "perfected" and made you can have some.

The capacitors for decoupling will have 3 SMT capacitors between the leads (100nF X7R, 4.7uF Murata Y5V / X7R, and a 220nF X7R with sizes to be looked into). So it'll have optimal decoupling (along with the 120uF panasonic FC). This configuration was researched at DIYaudio.com. I think the keywords were "Bypass IC decoupling capacitors".

Perhaps I'll have to integrate the output stage so that I don't have any problems, but I'm not sure that'd be what I want either. I don't know!

Thanks for the advice!

~Tom

 

[cetoole]

Have you run DRC yet, there are several traces that look like they wont pass, the most notible of which is the one from CHSL to switch, which seems to slightly intersect one of the pads of the X2 header.

 

[Nerull]

Ah, very good point cetoole, I'm going to pass by and use thinner traces to match up with the SMT pads anyway and clean up things a bit, but thanks for noticing that (it didn't come up on DRC actually

).

That could've been a not so good problem.

Thanks,

~Tom

 

[Nerull]

As I went to change my schematic to accommadate a ground plane on top, I looked at it and it created larger ground loops than if I were to use vias. The ground planes would almost be completely seperate sans for a few spaces on the edge of the board and narrow traces between the IC pins. The decoupling capacitors would also have to be placed further from the IC than would be recommended, and still would be seperate from each other (and would make a rather large loop). I think it would be best to keep this a 2-layer design, even if it does use vias for grounding under some circumstances.

~Tom

 

[00940]

The electrolytics used for bypass can be quite far apart of the chip. Only the small ceramics need to be right next to the pins of the pcm1794. With the groundplane on top, you can have very, very small ground loops using 0805 package.

 

[Nerull]

Quote:

Originally Posted by 00940 The electrolytics used for bypass can be quite far apart of the chip. Only the small ceramics need to be right next to the pins of the pcm1794. With the groundplane on top, you can have very, very small ground loops using 0805 package.

That's a good idea, and will implement that. I'm pretty glad that the electrolytics don't have to be so close.

Thanks for the advice!

~Tom

 

[Garbz]

Anotherthing that I just thought of, The top header is for IOut, and the Bottom for I2S or something isn't it?

The split ground plane idea will only work if the traces don't actually cross the plane. In each case you have 2 I2S traces on the digital side and 2 on the analogue side. Same with the IOut traces. If you don't want to move the connectors you can snake the ground plane around them accordingly.