[Garbz]

I've just finished my DAC and as smooth as the midrange is there's still something a bit bitey about the treble. Since i've ruled out jitter (75 ohm coax properly terminated into Jocko's 74hcu04 input buffer took care of that) i'm begining to think it's something still on the output stage. Fair enough it could be the PSU but I thought i'd ask this here anyway.

The DAC is PCM1730 http://focus.ti.com/lit/ds/symlink/pcm1730.pdf
8x oversampling
-82dB passband rejection

The current filter is nothing more then a cap over the opamp feedback loop. 2.2nf over 1.5k, followed by a further low-pass filter 1k and 3.3nf to eliminate all the stuff left. This gives a corner frequency of 48.2khz and 48.2khz respectively.

Since i'm about to play with the output stage anyway because it's too loud I need to adjust the cap regardless so I'm wondering if 48khz is ideal? The Datasheet sample filter (based on a 2 opamp design) uses 45khz as the corner frequency, yet i've seen some other DIY designs that are inherently lower.

The question is what corner frequency is ideal for the filter here?

 

[webzeb]

Quote:

Originally Posted by Garbz I've just finished my DAC and as smooth as the midrange is there's still something a bit bitey about the treble. Since i've ruled out jitter (75 ohm coax properly terminated into Jocko's 74hcu04 input buffer took care of that) i'm begining to think it's something still on the output stage. Fair enough it could be the PSU but I thought i'd ask this here anyway. The DAC is PCM1730 http://focus.ti.com/lit/ds/symlink/pcm1730.pdf 8x oversampling -82dB passband rejection The current filter is nothing more then a cap over the opamp feedback loop. 2.2nf over 1.5k, followed by a further low-pass filter 1k and 3.3nf to eliminate all the stuff left. This gives a corner frequency of 48.2khz and 48.2khz respectively. Since i'm about to play with the output stage anyway because it's too loud I need to adjust the cap regardless so I'm wondering if 48khz is ideal? The Datasheet sample filter (based on a 2 opamp design) uses 45khz as the corner frequency, yet i've seen some other DIY designs that are inherently lower. The question is what corner frequency is ideal for the filter here?

I'm sorry to deviate from the original subdject however I'm VERY interesting by this aspect.

Could you develop it, or give me some links where I could find some piece of information ?

Thanks.

Fred

 

[00940]

Could be the filter, the opamps, the PS. Difficult to say. For a 8X oversampling DAC, your filter sounds right.

 

[Wodgy]

48kHz is fine. You can move it an octave higher if you like. There's no reason to move it closer to the passband.

I would also experiment with eliminating the second op-amp stage. If it's doing balanced to single-ended conversion, just pull the signal off the positive side of the I/V stage.

Also, even though you've properly terminated the digital transmission line, you haven't ruled out jitter. All proper termination does is reduce added jitter from the transmission line. Transport jitter is still there in all its glory. You may want to experiment with different digital sources.

 

[Garbz]

An XO-3 clock is in route

That should nail it once and for all.

There is no second opamp. My dac outputs current relative to a 2.5V reference.
From there into an opamp to do I/V conversion and a filter to prevent digital noise being amped. Onto a low pass filter to remove the remainder of it. Then a resistor divider to bring the offset down, and finally into a single transistor follower (2sc1815) biased in class-A to the output. The signal remains fully balanced like the rest of my system.

I'm inclined to think that the problem is most likely the PSU and possibly still Jitter. Currently the prototype is running from a computer PSU. Asside from horrible switching noise proabaly effecting jitter performance the 3.3VA line of the PLL is linked directly to the 3.3VD line. Despite being regulated via an LM317 this was apparenlty bad according to the datasheet.

I just wanted to double check the filter since i need to change it anyway

 

[00940]

the LM317 is very bad at high frequencies (those really important for digital operation). Do you have ferrites on the supply lines ? The PLL is very sensitive to noise.

 

[Garbz]

Yes and no. i just tossed in the only value i had on hand. ... 10uH? Who knows. It's just temporary anyway. It's not the lm317 i'm concerned about it's the fact it's sharing it's supply line with all the logic devices on the board, and most importantly the 3.3VD line from the other side of the receiver. Datasheet states for jitter sensitive operations these must be seperately regulated.

I guess if it still sounds like this when the powersupply is finished i'll come crying back about the analogue stage