Hmm, lots of questions today!
Firstly, I have not said that 44.1/16 bit is better than HD PCM (its easily better than DSD IMHO - and this is an important requirement - on my DAC's). Probably the best recordings I have is 192/24 - and generally, all things being equal, higher SR is preferable - but not by much. In principle - and note I mean in an ideal world - 44.1/16 is capable of very much better performance than we currently get - with a large enough tap length, you can recover the timing perfectly, assuming the ADC has zero (and I do mean zero) aliasing which currently the pro ADC's do not have - its as bad as -6dB!. Moreover, properly dithered 16 bit is capable of perfectly resolving an infinitely small signal - if you take an infinite period of time to do the FFT or correlation. So the format is capable of, again in principle, of perfectly reproducing the original timing information and perfectly capable of accurately reproducing very small signals.
But "you know nothing Jon Snow" is my favourite quote,and until you do carefully structured and rigorous listening tests, this quote applies. One of the interesting things about the Davina project is being able to decimate 705.6 k to 44.1 without any aliasing at all. Couple that with a long tap length WTA filter on the DAC, then I can actually hear the losses involved and be able to actively minimise them. The next question is the effect of bit depth, and how to treat truncation without degrading sound-stage depth, and this will also be a very interesting test. Now its very easy to do it for a 16FS signal (as in Dave), you simply use a 350dB noise shaper - but this is not an option at 44.1
On to the noise shaper - the 350 dB limit is technology limited (and its a very complex story), given that I am using 20 elements on the pulse array. I could detect a change going from -330 to -350, but frankly it was small. Any more depth to wring out? Perhaps. But by far the biggest loss is on the analogue power amplifier - the digital power amp will solve it (I know as the early prototype had amazing depth reproduction). Then there is the issue of the ADC itself, and again we have Davina coming to the rescue, as I have already designed the ADC noise shaper and this exceeds 350 dB.
I mentioned tap length, and yes I suspect that longer tap lengths will give better sound. But by how much? Frankly I do not know, and its possible its not much. I have mentioned 1M taps before, as this gets us to a sinc function with an accuracy of better than 16 bits - this then guarantees time domain performance exceeding 16 bits accuracy for a 16FS output signal. Unfortunately, the FPGA's capable of doing this are insanely expensive.... And I shudder at the design time needed to write close to 1,000,000 lines of code and verify the design, let alone getting timing closure on the FPGA....
Electrostatic direct drive from a single stage pulse array DAC? Funny, John and I were talking about it today. I think he thought I could design one in an afternoon....
And talking of Jon Snow - season 6 Game of Thrones - not long to wait now.... Much less time to wait than designing an electrostatic DAC/amp, that's for sure.
Rob
For non-functional behavior, sure your IDE can generate code. But you don't gain anything other than saving time. It's not like it's actually going to do things. Re-using libraries on the other hand will help you gain time and functionality.
