00940
Headphoneus Supremus
- Joined
- Nov 6, 2002
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I know that... That's why it was under "problems".
Actually, I quoted the 48KHz from memory (coming from a diyaudio post). It's a bit more complex. Here are the relevant passage of the datasheet:
"The sample rate converter upsamples all different sample rates to XTALI/2, or 128 times the highest usable sample rate with 18-bit precision. This removes the need for complex PLL-based clocking schemes and allows almost unlimited sample rate accuracy with one fixed input clock frequency. With a 12.288 MHz clock, the DA converter operates at 128 x 48 kHz, i.e. 6.144 MHz, and creates a stereo in-phase analog signal. The oversampled output is low-pass filtered by an on-chip analog filter. This signal is then forwarded to the earphone amplifier."
"I2S CF MCLK ENA enables the MCLK output. The frequency is either directly the input clock (nominal 12.288 MHz), or half the input clock when mode register bit SM CLK RANGE is set to 1 (24-26 MHz input clock).
I2S CF SRATE controls the output samplerate. When set to 48 kHz, SCLK is MCLK divided by 8,when 96 kHz SCLK is MCLK divided by 4, and when 192 kHz SCLK is MCLK divided by 2."
Actually, I quoted the 48KHz from memory (coming from a diyaudio post). It's a bit more complex. Here are the relevant passage of the datasheet:
"The sample rate converter upsamples all different sample rates to XTALI/2, or 128 times the highest usable sample rate with 18-bit precision. This removes the need for complex PLL-based clocking schemes and allows almost unlimited sample rate accuracy with one fixed input clock frequency. With a 12.288 MHz clock, the DA converter operates at 128 x 48 kHz, i.e. 6.144 MHz, and creates a stereo in-phase analog signal. The oversampled output is low-pass filtered by an on-chip analog filter. This signal is then forwarded to the earphone amplifier."
"I2S CF MCLK ENA enables the MCLK output. The frequency is either directly the input clock (nominal 12.288 MHz), or half the input clock when mode register bit SM CLK RANGE is set to 1 (24-26 MHz input clock).
I2S CF SRATE controls the output samplerate. When set to 48 kHz, SCLK is MCLK divided by 8,when 96 kHz SCLK is MCLK divided by 4, and when 192 kHz SCLK is MCLK divided by 2."
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