Attempting to design/build an S/PDIF DAC
Apr 16, 2009 at 8:04 PM Post #16 of 20
That would seem to be personal preference.

Some people think that by using the SRC you can optimize the digital filters and possible reduce jitter . The opposite train of thought is that the less modification to the signal the better.
 
Apr 16, 2009 at 8:31 PM Post #17 of 20
I'm removing it then.
Less money, less effort, less room for error.

I'm pretty sure it isn't possible to remove jitter anyway. The output might use the crystal oscillator, but the input of the ASRC still uses the clock that's derived from the S/PDIF. It has to use this clock. There's no way around it unless you want to start dropping samples due to clock discrepancies.

Edit:
Maybe some kind of dynamic buffer could smooth it out a bit, but resampling the signal entirely seems unnecessary.
 
Apr 17, 2009 at 2:08 AM Post #19 of 20
As 00940 has pointed out, SRC do reduce jitter. But you do need a low jitter clock with a very clean power supply to fully realize all you can do there.

I've done one DAC design. Even with all the checking that I did the first time around, I still messed up a bunch of stuff. If you willing to do evolutions, then building one without SRC the first time gets the experience under your belt. Then when you add SRC, you also have a benchmark that you are comparing against.
 
Apr 23, 2009 at 6:55 PM Post #20 of 20
In an effort to simplify the design and reduce the cost I've replaced the DIR9001/SRC4193 with a WM8804 (~$3 and it supposedly has excellent clock recovery), replaced the PCM1792 with the PCM1798, and removed the MCU altogether. I also added damping resistors to the I2S lines.

Schematic


I might remove the differential stage, that way I can feed the output of the I/V stage into an external amp over two twisted pairs and get better common mode rejection.

Edit:
Just noticed that all my op-amps are backwards. They're all Schmitt triggers instead of I/V converters :[
I don't know how I overlooked it before, but it's fixed now.
 

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