b0dhi
Headphoneus Supremus
- Joined
- Oct 12, 2005
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To give a bit of background to this question, I'm planning to build a DAC based around the TDA1541A. One of the goals is to have an absolute minimum of jitter. So my clock will be an oscillator going straight to the DAC chip with nothing in between. The connection will be via ethernet to my computer, which will be slaved to the DAC.
In the datasheet (here) you can see the chip can take in data in 2 formats. One of them, it seems, uses the word clock to operate the output latch. The other way is to trigger the Latch Enable manually.
Seems to me that the logic used to generate the Latch Enable from the wordclock must add some jitter, so I want to manually operate the latch, if possible.
The datasheet, though, seems to indicate that the LE needs to stay high 0ns. Zero nanoseconds. What the? That can't be right can it?
Has anyone used the TDA1541/A using the latch enable and understands what this means?
Thanks
In the datasheet (here) you can see the chip can take in data in 2 formats. One of them, it seems, uses the word clock to operate the output latch. The other way is to trigger the Latch Enable manually.
Seems to me that the logic used to generate the Latch Enable from the wordclock must add some jitter, so I want to manually operate the latch, if possible.
The datasheet, though, seems to indicate that the LE needs to stay high 0ns. Zero nanoseconds. What the? That can't be right can it?
Has anyone used the TDA1541/A using the latch enable and understands what this means?
Thanks
