[Kermy]

Hey guys, trying to fab a PIMETA PCB for my Elec. Manuf class. We're using Orcad so right now I'm about done with the schematic part. I was wondering if you guys could double check my schematic before I do the layout.

I'm worried about the pin configuration and the fact that for the Left and Right channels, between the two JFETs, Orcad gives me a "No driving source" when I do a DRC check.

http://www.calpoly.edu/~hema/Sch1.JPG
http://www.calpoly.edu/~hema/Sch2.JPG

Edit: See reply below

 

[flecom]

looks fine to me... maybe the 0 ohm and inf ohm resistors are freaking out your app?

 

[jnewman]

Quote:

Originally Posted by Kermy Hey guys, trying to fab a PIMETA PCB for my Elec. Manuf class. We're using Orcad so right now I'm about done with the schematic part. I was wondering if you guys could double check my schematic before I do the layout. I'm worried about the pin configuration and the fact that for the Left and Right channels, between the two JFETs, Orcad gives me a "No driving source" when I do a DRC check. http://www.calpoly.edu/~hema/Sch1.JPG http://www.calpoly.edu/~hema/Sch2.JPG

Your schematic looks correct to me... the problem may be arising if you are putting identical JFETs in the schematic - they VERY specifically must have different limiting currents (although they can be same model, they MUST be matched so that your Q2's limiting current is greater than that of your Q3). You could also fix this by using, for example, a 2N5486 for Q2 and a 2N5484 for your Q3.

 

[tangent]

That's what you get for relying on SPICE with no idea what SPICE is doing. And once you know what SPICE is doing, you don't need SPICE much.

Here endeth the lesson.

 

[MisterX]

Mind if I ask What?

You're taking a redly available schematic of an existing "commercial" design and redrawing it?
Then you design another board for it?
Isn't this kinda like cheating?
If you are gonna do this swap the buffers or something.
A differential opamp based amplifier board that accepts the Intersill HA3-5002-5 buffers would be kinda cool.

Or better yet incorporate a discrete buffer into your design and walk away from this project with something that would look very impressive on your resume.

 

[Kermy]

Hehe yea it would be cheating if I was an EE or this was a circuit design class. But I'm in Manufacturing Engineering and this is sorta of a "survey" class on how PCBs, electronics are produced. They just want to show us how they fab the boards, solder (wave, smt, etc) and such. If it was circuit design though...yea big time cheating.

The project is everyone buys a kit, or finds one online, use Orcad to draw the schematic in and then layout the traces. Then fab the boards, solder the components, make your own DIY enclosure and present it.

Wish I could just buy the board from Tangent though. Save me so much time and grief. But darn the luck! I can't!

 

[MisterX]

See what I get for assuming you meant EE instead of another type of train driver.

 

[Kermy]

Well the schematic's almost ready for layout. Can anyone do one more pass? Only error is that the rail splitter is connected to power. Though, think it's not really an error.

Here's the new links:
http://www.calpoly.edu/~hema/sch1.jpg
http://www.calpoly.edu/~hema/sch2.jpg

 

[amb]

Your cascoded JFET current source is labeled wrong, the 2N5486 should be the top one. This doesn't impact pcb layout but you should make sure you install them correctly.