[Dreamslacker]

Quote:

Originally Posted by ppl I am uncleer as to the 6 volts of drop is that across the resistors or the fets. 6ma across 10 ohms is 60 mV not 6 volts. if you are indeed getting 6 volts arcoss the 10 ohm resistors are nor your opamps smokin after power up and is this amp actualy working and reproducing cleen undistorted sound? what about the TLE rail splitters are thay also not burnning hot.

Yes. It did seem wierd to me as well since 0.6A would send the opamps into shutdown and fry the isolation resistors.
But then I haven't seen his work personally so I can make anything out of it.

 

[zhoufang]

sorry for the confusion, it's a typo.
The voltage drop across the 10ohm resistors are 60mV.
the voltage drop across J-fets are around 5V.

 

[morsel]

I'm with Dreamslacker. Check your FETs. Make sure your pdf is from the company that made your FETs, as pin assignments vary between manufacturers even for the same part number.

 

[zhoufang]

I used 2 2N5486 per rail as in the officail PPA Schematic.
Due to the source I get it I have no way to know who's the manufacturer.
all I can see on the flat surface is

.2N
5486
144

the last line 144 is in smaller font.
There's no logo or whatever.
the three legs are straight in one line.
Anyone knows who made these?

I didn't even bother what the 3 legs are.
All I did was look at the picture of the PPA PCB from Tangent's website, did some transformation (that did not change the connection) and laydown my own PCB layout. I rechecked the transformation part several times.

When I checked for the Idss I used the layout that's as in my final design (on solderless test board). short with 8V (from half dead 9V battery) and 10mA-12.5mA passed through. If I got the 3 legs wrong could I this get this kind of results? (I don't quite understand discrete transistors so need someone to help me on this)

 

[amb]

If your 2N5486s are the "standard" Fairchild pinouts, it should be drain-source-gate, from left to right and looking at the flat face of the transistor with the pins pointed down. On the PPA, each of these should have the gate and and source tied together, on the positive rail, the drain should be on the Vb side of the power rail, and the source/gate should be on the Vi side (See PPA schematic). On the negative rail, it's the opposite. Check your wiring.

 

[zhoufang]

Quote:

Originally Posted by amb If your 2N5486s are the "standard" Fairchild pinouts, it should be drain-source-gate, from left to right and looking at the flat face of the transistor with the pins pointed down. On the PPA, each of these should have the gate and and source tied together, on the positive rail, the drain should be on the Vb side of the power rail, and the source/gate should be on the Vi side (See PPA schematic). On the negative rail, it's the opposite. Check your wiring.

I see that the offical PPA PCB is designed for FETs with the "standard" Fairchild pinouts.
So if my FET follows it I should be fine.
Since the PPA have the gate and and source tied together, I only need to get the drain right.

Is there anyway to test the pinout of J-fets (I only found tutorial on NPN & PNP)?

It will also be great if someone will tell me that whether I could be in the current situation if I will be in one of the following ways of being wrong(since 2 pins are tied together, only 3 combi is possible with one being the right one):
1. have the drain and and source tied together
2. have the gate and and drain tied together


PS:
I just checked the Class-A biasing section of the amp.
It follows the Official PPA schematic and is built with 2N5486 & 2N5484. The 2N5486 are the same as those used for rail isolation and the design also have the same assumption for pin layout (i.e. the normal type).
The result is that the section works fine. With current variaing between 0mA to the Idss I measured for 2N5484 (about 2.3mA) as I turn the var resistor.
I guess I couldn't have get it working if I get the pin layout wrong.

Could it be that this manufacturer's J-fet just behave different from others?

 

[amb]

Since your cascode JFET current source works fine, if the 2N5486s there is the same manufacturer as the ones on your rail splitter, then you should be fine as far as pinouts are concerned.

Just to verify that those rail isolation JFETs are actually dropping an abnormal amount of voltage... Measure the voltage across pins 7 and 4 on each of your opamps. What do you get? And what is the voltage across pins 1 and 5 of the HA5002 buffers?

 

[zhoufang]

I did measure the rail-to-rail voltage across the op-amps.
It is consistant with the rail-to-rail voltage before the J-FET - 2*(voltage drop per rail).
So I started with about 20V (16 X AA) and only less than 9V goes to the op-amp even at the begaining of battery life.
Tangent said that The performance of OPA627/637 falls off a cliff when voltage drop below 9V. Well thought I don't hear any distorted sound until the voltage across op-amp drop to below 7V, I will be adding another 8 cells to the battery pack. (even then the op-amp never get more than 19V, maybe with this kind of voltages the AD8610/8066 will work better)

Thanks for everyone's help here, I looks like my J-FETs just have different property from others.

 

[morsel]

Losing over 5V per rail is unacceptable. If you can't get FETs that work properly, try replacing them with 10 Ohm resistors.

 

[zhoufang]

as I was not getting enough voltage to OPAs, I increase the battery pack from 16 cells to 24 NiMH cells. So the total voltage is around 30V (+-15V, just right for OPA627/637).
As I did that the J-fets eats more voltages, taking around 9-11V per rail. So I was still getting less than 10V rail-ro-rail across the OPA.
By this point I knew Something is wrong. The test of Idss showed that each the two 2N5456 per rail together can pass through >20mA with a voltage drop of 8V, now I'm passing through <7mA and lossing up to 11V!

so I desoldered a point and did some test.
The current passing through the 10ohm R8s are indeed 6-7mA, but the current through each rail of Q3 J-fets are 21mA!
Later I found it's the TLE2426 that's eating about 15mA each (could have been more, it just saturates the Q3 J-FETs)!

I was using the 8Pin SOIC TLE with the noise reduction pin.
I connected the 1uF noise reduction cap across NR pin and Vout pin, while the right way should be across NR pin and the V- pin.
The TI's datasheet did not really show how the Cnr should be connected, and I made a wrong assumption.

After correcting this, the voltage drop per rail droped to between 0.5V to 0.7V, normal.
So It was a TLE problem, not a J-FET problem.

Thanks again to all those who have help to answer my query!

 

[morsel]

Interesting problem. Congratulations on fixing your amp.