https://www.mola-mola.nl/dac.php
"The converter is a two board stack that fits into one of the option slots in the preamp. On the first board, all incoming digital audio is upsampled to 3.125MHz/32 bits and converted to noise shaped PWM. On the other board are two mono DACs, in which a discrete 32- stage FIR DAC and a single-stage 4th order filtering I/V converter, convert the PWM...
...extraordinary care has been taken to deal with jitter. Mola Mola’s DAC uses a home-grown asynchronous upsampling algorithm whose input frequency measurement slows down rapidly until after a few seconds of lock, the frequency ratio measurement is frozen. Frequency stability is then wholly determined by the internal clock, a laboratory grade 100MHz SC-cut oscillator. This is effectively an atomic clock sans the physics package"
Hi-Fi news:
"Mola-Mola’s software upsamples all incoming data to 3.125MHz, truncating the wordlength to 5-bits while using a 7th-order noise-shaper to retain full dynamic range right up to 80kHz. Each 5-bit digital ‘word’ is sufficient to describe one of 32 possible pulse widths that, in turn, describe the amplitude of the audio signal on an (over)sample-by-sample basis. The pulses vary in steps of 10nsec (the system clock is 100MHz) right up to a full width of 320nsec (0.32µsec). This Pulse Width Modulated (PWM) signal is fed into a 32-stage shift register, clocked at 100MHz, so a composite of 32 pulses ends up reproducing the full PWM signal every 10nsec.
The 32 outputs of the register are summed together so that the final DAC output is the moving average of the PWM signal over consecutive blocks of
32 clock cycles (ie, one PWM cycle), updating every 10nsec. The PWM signal is ‘conditioned’ by a comb filter whose teeth coincide exactly with the 3.125MHz repetition rate. Mola-Mola could have used the signal from any of the 32 outputs alone and simply low-pass filtered it. Instead, the moving average technique not only overcomes any slight mis-match in the summing resistors but it also removes the PWM carrier that could potentially demodulate clock jitter down into the audio band."
Stereophile (B. Putzeys words):
"Compared to the state of the art, I had quite a shopping list of things I wanted to get right, but the absolute number one item was a completely signal-independent noise floor. If the noise floor modulates, that immediately gives the sound away as 'digital.' If you want to see a typical sigma-delta converter at its worst, feed it a constant code (ie DC). Some DC values produce clearly audible whistles. If you want to tease an R2R DAC in a similar manner, feed it a ramp signal. I wanted something where the noise floor is truly just a steady hiss, no matter what signal you put in. This is what drove the choice of single-edge PWM as the digital intermediate code.
"As luck would have it, I'd invented precisely such a modulator in 2004 as a mathematical stunt with no particular application in mind, but that it might be useful for a converter was clear even then. I filed away the idea, waiting for an excuse to make a DAC. That came when we started demoing with the Makua and Kalugas [Mola's pre and power amplifiers, respectively] and had trouble finding a converter that would show off the quality of the system without multiplying the price of the whole setup....So, a DAC project got under way in 2013.
"Initially, I looked at using only a single, high-current switch to convert the PWM signal, but it soon struck me that running a number of them in a
time-staggered fashion would allow me to remove most of the PWM carrier right away and so reduce noise. That was the core of the design. The
remainder of the project was being completely anal about all the other stages of the converter: digital filtering, clocking, and analogue-output filtering.
"Of those, only the digital filter needed to be optimized by ear. It's pretty obvious that a more stable clock is more ideal, and an output filter with lower noise and distortion is also more ideal. But there's no ideal upsampling filter, a priori: The ear is not a spectrum analyzer. You need to listen to original high-rez files, filter them down, upsample them again, and then hear which kind of filter chain leaves the smallest sonic fingerprint. That is to say, how do you get from high-rez to (eg) "Red Book" and back whilst getting the smallest possible audible change? And then it turns out that a lot of filters out there sound really impressive, but only because they're heavily euphonic—not because they're sonically neutral....To make matters worse, the optimum design differs for different sampling rates....
"Clocking was addressed using a very stable, non-adjustable crystal oscillator—adjustable ones are quite noisy—and synchronizing the signal using a homegrown asynchronous sample-rate converter that forms part of the digital filter. How that was done is a story in its own right, but it might take us a bit far [afield]. Same for the analogue output filter stage, which is also rather original in its conception. So, as much as you'd like to know what the magic ingredient is, I can only tell you that it's about getting all the parts right, not just individually but as a system. t's not sexy, but then real engineering rarely is."
ASR (B. Putzeys words):
"In case anyone's wondering why I decided to go discrete, I actually started testing existing sigma-delta DAC chips first but could find none that didn't have idle tones. I suspect that is still the case. Chip manufacturers usually manage to move these out of the band at mid-scale (i.e. zero or small signal), but they show up in a THD vs level graph as a small increase in apparent noise typically starting at -20dBfs. Basically this "noise" are tones that are swept in and out of the audio band, frequency modulated by the signal. The simplest way of testing for this is to do a noise level vs DC input plot. The tones, when they appear, are well above the noise floor, even as integrated over the audio band. Using PWM as a conversion format solves this tone problem, but nobody is doing that on an IC. Hence the discrete design. I won't speculate on the audibility of this phenomenon but anything that is measurable is fair game for me. If people are going to shell out serious moolah for a DAC, least thing you can do is show an objectively provable benefit. Low jitter is also something I like to that's why we ended up coding our own ASRC algorithm."
"All ADCs/DACs have some sort internal data format that is used to get from digital to analogue. The converter circuit and the internal format are chosen together, depending on the designer's judgment or expectation of which combo is optimal. There are only two cases where the internal format coincides with an existing audio format. On one extreme are R2R DACs that directly convert the PCM data you feed them by controlling 24 switchable current sources, each of which has half the current of the previous one. On the other extreme sit 1-bit converters that switch a single current or voltage source but at a high sampling rate. Both these extremes have limitations and the most common choice these days is a kind of compromise. They use a small number of bits (typically 5) that are used to control 32 (2^5) current sources with nominally equal currents, plus some trick to make the conversion minimally sensitive to any imbalances in those currents. The Tambaqui sits more or less in this camp: the PWM signal has a switching frequency of 3.125MHz, and can take 33 discrete lengths from 0*10ns to 32*10ns. So it's basically a 5-bit, 3.125MHz converter. The choice for PWM was given by the need to get rid of those idle tones I mentioned."
EAR (B. Putzeys words):
“I would have been happy to cobble it together from standard DAC chips etc, if there had been any way it would have checked off my complete shopping list:
1) No noise floor modulation.
2) Negligible distortion from tiny signal levels up to full output.
3) Jitter elimination down to very low frequencies.
4) Digital filters with negligible in-band ripple (i.e. no pre-echo).
5) Digital filters with moderately slow transition (i.e. reasonably short ring tails).
No DAC chip fulfils the first item in the list and no ASRC does the third (a discrete PLL without SRC conceivably could be built). The remaining three don’t seem to occur together in any standard chipset I could find. I was simply forced to take the long way round.
The entire story about how exactly it’s done is for geeks, but for me the secret is realising the importance of all five items mentioned above and getting them sorted by whatever means.”
Audiophilestyle (Mola DAC vs Chord DAVE thread):
The upsampler and modulator are written in software. The upsampler is an asynchronous sample rate converter. You can also buy chips that do that but they only come with "just good enough" filter responses and neither do they have a particularly narrow PLL bandwidth so there was no alternative left but build one from the ground up. The choice for asynchronous vs using multiple clock crystals was made because you can't make a tuneable oscillator with the extremely stable SC cut crystal that MM use.
Far from being hard coded, the entire thing is completely software defined. OTOH the user has no say in what type of filter it uses, it being felt that allowing users to toy with it was a gimmick, since for every input rate there can only be one filter setting that is least audible (the filters change with input rate and format). It follows that any one might add just for the sake of "giving users a choice" would be more audible.
The modulator is PWM and is based on a scheme invented in 2004 to generate noise shaped PWM. It should be noted that it's not an n-bit noise shaper followed by a conversion to PWM but the PWM is noise shaped directly. Of course, from an information perspective we're still looking at the equivalent of 5 bits at 3.125 MHz however you want to look at it. The gory details are in
https://www.hypex.nl/img/upload/doc/an_wp/WP_AES120BP_Simple_ultralow_distortion_digital_PWM.pdf
What sets this type of PWM aside from ordinary 1-bit sigmadelta is that it is inherently free from intersymbol interference. If you reproduce a 1-bit signal using a switching circuit whose rising and falling edges aren't exactly symmetrical you get a distortion component equal to the number of 1/0 transitions per second, which varies with the signal and which has tone like components. With the single-edged PWM conversion the number of transitions per second is constant and only one of the two edges encodes a signal so the same rising/falling asymmetry would cause nothing worse than a tiny amount of DC offset. This observation was first made by Peter Craven in 1993, who was then trying to design a DAC for B&W and published a way of generating such a signal. So if you are looking for a historical precedent for using PWM in a DAC, that is the closest you'll get. If you compare Craven's paper (
http://www.aes.org/e-lib/browse.cfm?elib=7001 ) with the one linked above you can see the new method is significantly more straightforward and has lower distortion.
The FIR trick is this: if you generate a clocked PWM signal with a period of N clock cycles, and you run that through a FIR filter with N equal valued coefficients, the output of that FIR filter is simply the total number of ones over the past full cycle. This removes the PWM switching frequency and some shaped noise from the output signal, making life easier on the analogue filter that follows. The resistors need not be matched since each tap sees the complete signal. A mismatch only slightly affects the attenuation of the 3.125MHz component. This is why FIR DACs are used. They have been around in some form or other since the mid 90's. I'm not sure about other commercially available PWM based FIR DACs though.
Yes yes yes, diminishing returns etc etc etc., I accept that. What I can't accept is realising a month after purchase that I can't really hear that much difference after all. Do other forum members have any personal experience going from something Node-tier to Mola Mola-land?
