Every stand-alone DAC I'm aware of has some type of I2S interface. I can't think of any that have straight S/PIDF because there is a fair amount of work involved in recovering the data from the stream. The device that does that job is called a Digital Receiver. A good example is the CS8416. This is the device you're missing from your computer->DAC chain. I assume you're refering to a DAC IC and not a piece of stereo equipment? At any rate, your computer does not normally output I2S to my knowledge.
The long answer:
S/PIDF is a 1 wire method of digital transmission of audio data. The clock is embedded into the data and is known as a bi-phase code. The data's Ones and Zeros are represented by the spacing of level (0->1->0) transitions in the signal. Packing and unpacking data into s/pidf (also sometimes called EIAJ) is a jittery process. I have the exact numbers for the specification somwhere but can't find them. The specification does mandate that a receiver chip have a certain jitter-rejection capability to account for the added jitter. The spec is, in theory, such that the recovered clock's jitter is below the smallest representable digital value being transmitted, ie not perceptible. We all know this isn't quite true though. S/PIDF is usually implemented over the longer connections from transport mechanism to DAC board. It is not commonly used elsewhere in a CD player, etc for moving data around locally.
I2S (the 2 is actually for "squared": sometimes it's written IIS) is a three wire serial interface. I've never been exactly sure on this part myself, but I believe I2S has additional requirements over just the standard 3 wire interface. But they can be compatable as far as I know. When I mention I2S from here on I'm refering to the concept, not the exact spec.
It is used exactly where S/PIDF isn't: local area transmission. That's not to say it can't be used over distances too, it's just not as common. I believe that the I2S signal is more prone to transmission jitter than s/pidf is, but s/pidf's reclocking jitter kind of offsets it I suppose. Not sure which one would win.
So, as mentioned in an above post, you have Data, Bit Clock, and Word Clock. The wclk runs at some multiple of the sampling rate. A stereo-pair of samples are transmitted on the data line in every wclk period. When wclk is high, you're getting one channel's samples, when it's low your'e getting the other channel. The bclk runs at a multiple of the wclk. The difference is at least 32x which is equivalent to 2 16-bit samples per wclk period. The data signal is simply high on a bit clock transition for a One and low on a transition for Zero. The wclk is there to mark where the samples begin and end in the serial stream. The details of this can change quite a bit, and that is where I'm not sure what is truely considered I2S.
