kipman725
500+ Head-Fier
- Joined
- Nov 6, 2006
- Posts
- 530
- Likes
- 11
My I2S clock is going to have 2nS jitter I think this is unacceptably high so I will use a pll to generate a clock with less short term jitter. Doing some rough calculations for 16bit accuracy in the time domain I require a jitter of <5pS?!? this seems smaller than is possible, I will go through how I worked this out so you can point out my mistake:
1. used 64* sample rate as I2S clock freq: 2.82E6
2. 1/ to get time period of clock
3. divide by 2^16
4. 5.4E-12 :S
hmm looks like I will be designing my own PLL as all the IC's I find deal with >10Mbit/s but shouldn't be as hard as I initially thought, I could probably get it down to about 150pS jitter. Or less if I compromise on supported sample rates.
1. used 64* sample rate as I2S clock freq: 2.82E6
2. 1/ to get time period of clock
3. divide by 2^16
4. 5.4E-12 :S
hmm looks like I will be designing my own PLL as all the IC's I find deal with >10Mbit/s but shouldn't be as hard as I initially thought, I could probably get it down to about 150pS jitter. Or less if I compromise on supported sample rates.
