Does 0404 DSP resample 44.1Khz->48Khz?
Nov 6, 2004 at 6:53 PM Thread Starter Post #1 of 65

gaboo

100+ Head-Fier
Joined
Apr 20, 2004
Posts
465
Likes
0
It seem the consensus on this board is that E-MU 0404 (unlike its more expensive brethren) uses a single clock for the 10K2 DSP.

The interesting questions is: does the 10K2 DSP resample 44.1->48Khz when applying effects? Or is the DSP clock actually set 44.1Khz somehow?
 
Nov 6, 2004 at 7:37 PM Post #3 of 65
Quote:

Originally Posted by maarek99
I remember that Ichi has told us the 0404 doesn't resample.


Unless he told you in a private conversation, can you provide a link?
 
Nov 6, 2004 at 7:39 PM Post #4 of 65
re: effects. how do you test if it resamples or not?
 
Nov 6, 2004 at 7:59 PM Post #5 of 65
running it's digital output to somewhere you can see what's the samplerate of it..
 
Nov 6, 2004 at 8:08 PM Post #6 of 65
Quote:

Originally Posted by Glassman
running it's digital output to somewhere you can see what's the samplerate of it..


You mean the DSP output, right? The card output can obviously be set independently of DPS output, 96Khz wouldn't work otherwise...

Probably the simplest way would be to apply a null efect, e.g. an EQ set to 0dB (not bypassed!) and see if the DSP output data is bit perfectly equal the input.
Given that you can use the DSP in ASIO apps (i.e. send an receive the data on the PCI bus), it should be simple to do it without even taking the signal out from the card. Given the internal 67bit precision of the 10K2 there should probably be no differences for a null effect.
 
Nov 6, 2004 at 8:17 PM Post #7 of 65
I was talking more about s/pdif output, since the ability to run 44.1 clock is the key, not 10k2's ability to work with it, it can safely run at it's 48 and the FPGA will take care of arranging the stream for 44.1 output.. all we need is the appropriate clock and that can be derived from the 48 oscillator, because the ratio is just 441:480 so you basicaly implement a counter which nulls itself after receiving 441 ticks, certainly an easy thing.. having separate oscillator for both however must be somewhat better, otherwise they wouldn't bothered to use it on 1010..
 
Nov 6, 2004 at 8:24 PM Post #8 of 65
You would not want to base a clock off a counter implemented in a FPGA. The jitter specs would be pretty bad.

You could do it using a PLL or DLL with the division ratio you mentioned.

Does anyone know if the 0404 uses an FPGA and if so model?
 
Nov 6, 2004 at 8:30 PM Post #9 of 65
I haven't checked which one is it, but it pretty much has to be FPGA and you're right, PLL is much better and usually there's some already included in FPGAs.. but yes, it's all about jitter vs. costs..
 
Nov 6, 2004 at 8:48 PM Post #10 of 65
Quote:

Originally Posted by Glassman
I was talking more about s/pdif output, since the ability to run 44.1 clock is the key, not 10k2's ability to work with it, it can safely run at it's 48 and the FPGA will take care of arranging the stream for 44.1 output.. all we need is the appropriate clock and that can be derived from the 48 oscillator, because the ratio is just 441:480 so you basicaly implement a counter which nulls itself after receiving 441 ticks, certainly an easy thing.. having separate oscillator for both however must be somewhat better, otherwise they wouldn't bothered to use it on 1010..


The 0404 card can definetly output at 44.1Khz on all digital outputs, it's in the specs.

But that doesn't mean the DSP clock is ever set at freq... Look at Audigy 2. The P16V chip can be set to 44.1 sampling despite the 10K2 being stuck at 48Khz. Unfortunately, it's a mistery what happens then to card outputs. One of these days I'll measure the outputs using the P16V Linux driver [but I have to move my home machine to work]...

Granted, given that 0404 is pro card, it's far more likely that they use a clock divider rather that the A2 "solution". Still inquiring minds need proof.
evil_smiley.gif
 
Nov 6, 2004 at 8:50 PM Post #11 of 65
Quote:

Originally Posted by Lilac_Wine
You would not want to base a clock off a counter implemented in a FPGA. The jitter specs would be pretty bad.

You could do it using a PLL or DLL with the division ratio you mentioned.



So, the most likely disadvantage of 0404 vs 1010 is increased jitter due to the clock divider at 44.1Khz?

Quote:

Does anyone know if the 0404 uses an FPGA and if so model?


It's a Xilinx Spartan II most likely. That's what 1010 uses: XC2S50E-6C (pic). I haven't seen pics of 0404 with the stickers off.
 
Nov 6, 2004 at 8:56 PM Post #12 of 65
I believe that a Xilinx Spartan uses DLLs instead of PLLs. DLLs are more likely to multiply the input jitter, whereas a PLL tends to act like a lowpass filter.

They could also be using a descrete PLL.
 
Nov 6, 2004 at 8:59 PM Post #14 of 65
Quote:

Originally Posted by Distroyed
1010? Ref. 1212m?


1010 is the PCI card common to 1212m, 1820 and 1820m DAS products.
 
Nov 6, 2004 at 9:08 PM Post #15 of 65
Quote:

Originally Posted by Lilac_Wine
I believe that a Xilinx Spartan uses DLLs instead of PLLs. DLLs are more likely to multiply the input jitter, whereas a PLL tends to act like a lowpass filter.


Confirmed. There are 4 DLLs on the chip. Spec sheet.
But those seem to be used internally, I don't know if you can use them as clock source for another chip.
confused.gif


Quote:

They could also be using a descrete PLL.


Ya' never know.
evil_smiley.gif
 

Users who are viewing this thread

Back
Top