[TzeYang]

Since my lecturers are too "busy" to answer me anything unrelated to my course subjects, I have no choice but to ask my questions here.

HeadWize - Project: A Pure Class A Dynamic Headphone Amplifier by Kevin Gilmore

I'll use the Dynalo as an example because I'm working on something similar and i need to reconfirm my maths.

Gilmore says that the open loop gain of the amplifier is about 35dB, which translates to a gain of about 56.2

So let's start from the 1st stage.
Assume Vbe = 0.65

Input Stage:

Tail current is about 2mA, given by the formula Iq = (1.6V-0.65V)/500 Ohm.

Each JFET will then run at 1mA each. 5k drain resistor and 200 source resistor means there will be a gain of 25, given by formula Av = 5000 Ohm/200 Ohm (similar to Rc/Re in BJT circuits).

This is a differential input stage, meaning we have to double the voltage amplification, which in the end gives us a gain of 50 at the input differential stage.

VAS Stage:

We have 1mA current through each of the JFETs. V = IR. So we have about 5 Volts across each of the 5k drain resistors.

The generated bias voltage will then bias the BJTs on the 2nd VAS Stage. Since we have 1k emitter resistor on the BJT stage, so we have about 4.3mA running through them given by the formula Iq = (5V - 0.65V)/1000 Ohm.

There is a 510 Ohm collector resistor on the VAS stage so the gain on this stage is 0.5 given by the formula Av = 510 Ohm/1000 Ohm.

Ultimately, we have about a gain of 75, given by the equation Total Av = 50 + 0.5*50 = ~75.

Using Gain to dB Formula, we have about 37dB of total gain, given by the formula dB = 20 log (gain) (well it's close enough, i know something is wrong with this stage's calculation so please help me thanks XD)

Output stage Bias current calculation:

We have 4.3mA running on the VAS Stage. Which means we also have 4.3mA running through the 510 Ohm Resistor. V = IR = 0.0043 x 510 = 2.193V voltage drop across the resistor. Since we have 50 Ohm of emitter resistor, Iq = (2.193 - 0.65*2)/50 = 30mA on each pair of the output stage. Which means about 15mA on each transistor.



Can someone please check if I'm right or wrong? Also, let's say the 510Ohm resistor is replaced by a VBE Multiplier circuit instead, will it be affecting the gain of the amplifier if we bias the output stage using the VBE Multiplier? (meaning it's no longer consistent)

 

[nikongod]

The good DR is known for designing circuits on place mats at restaurants, sometimes his math is off a little. you should not attempt to look at any schematic he posted on dialup. you could design it yourself before it downloads. he likes big pictures. like the kind of scans where you can see the pulp of the paper...

He said the open-loop gain is 35 (voltage gain) NOT DB

anyways, im open for correction but:
The signal is effectively split in half again between the second stage and the output stage. This with the 0.9 gain of the output stage accounts for getting a voltage gain of 75, where he got 35.