[wakibaki]

 
Voltage sources are all 1.5V.
 
w

 

[wdiabc]

Quote:

 
Voltage sources are all 1.5V.
 
w

Thank you very much for your help running the simulation. looks great to me. I dont know how THD is measured but 1.6% is a lot. I am looking to optimize it by altering the resistor values. I set up this circuit last night for a quick listen and some tests shows resistor value can greatly impact the output. Do you have any thoughts and comments about the circuit? Thanks!

 

[kevin gilmore]

an open loop circuit like this with that much voltage gain...
1.6% thd is very reasonable. Adding a differential cascade
at the bottom is going to help a bunch.

 

[wakibaki]

The swings you are seeing there, ~150V pk-pk, are using 2N3904 transistor model throughout. The simulator doesn't care that 2N3904 blows up, it doesn't tell me that, just carries on regardless.
 
When I put in TIP50 + 2N2222, things get much worse. Swing falls to +/-90V, THD goes way up. I increased the drive to 2.5V pk-pk and moved the quiescent voltage to ~180V (you can see the increasing assymmetry, with compression of the sinewave on the negative half of the cycle), to get 211V pk-pk out at ~5.5% THD.
 
Things are slightly better when output is taken from the bottom of R3 & R4, drive must be increased again (to ~2.7V pk-pk) to get 211V pk-pk out, but THD is better at ~4.5%.
 
I tried to attach the schematic so you can run the simulation yourself, both as a .txt file and as a .zip, but the forum is not cooperating.
 
I am not entirely happy with the circuit, I don't feel I understand what is going on in it. I don't like having two current sources feeding a current sink. This means that the circuit is very tightly balanced with just the base currents of the LTP making up any difference in current, and the quiescent point setting is very critical. I can't help but feel that it will not be very stable with temperature.
 
I was a programmer and then an FPGA designer, I came to discrete audio design via software radio, RF design and only latterly IC audio design. Since ill-health forced my retirement this has been a good way to stay out of trouble, but you will get better advice from some of these guys who have been doing it longer than I.
 
w

 

[wdiabc]

Quote:

The swings you are seeing there, ~150V pk-pk, are using 2N3904 transistor model throughout. The simulator doesn't care that 2N3904 blows up, it doesn't tell me that, just carries on regardless.
 
When I put in TIP50 + 2N2222, things get much worse. Swing falls to +/-90V, THD goes way up. I increased the drive to 2.5V pk-pk and moved the quiescent voltage to ~180V (you can see the increasing assymmetry, with compression of the sinewave on the negative half of the cycle), to get 211V pk-pk out at ~5.5% THD.
 
Things are slightly better when output is taken from the bottom of R3 & R4, drive must be increased again (to ~2.7V pk-pk) to get 211V pk-pk out, but THD is better at ~4.5%.
 
I tried to attach the schematic so you can run the simulation yourself, both as a .txt file and as a .zip, but the forum is not cooperating.
 
I am not entirely happy with the circuit, I don't feel I understand what is going on in it. I don't like having two current sources feeding a current sink. This means that the circuit is very tightly balanced with just the base currents of the LTP making up any difference in current, and the quiescent point setting is very critical. I can't help but feel that it will not be very stable with temperature.
 
I was a programmer and then an FPGA designer, I came to discrete audio design via software radio, RF design and only latterly IC audio design. Since ill-health forced my retirement this has been a good way to stay out of trouble, but you will get better advice from some of these guys who have been doing it longer than I.
 
w

thank you for your comments. I built the circuit using actual transistors and resistors as shown in the circuit, and based on my experience, once adjusted, the bias is pretty stable and will not drift that much ( Once adjusted, within in 60 seconds the DC output will move up and down a little before transistors warms up but later become pretty stable at 1/2 of V supply) This circuit is basically a transistor version of SRPP and actual listening shows I really like the sound, much smoother, better clarity and better base definition,  compared to the sound from TA2020 amp + the stock SRD7. 

 

[wakibaki]

Tried a lot of variations on this. I found the spice model for IXCP10M90S (strictly speaking a regulator) is just a MOSFET.
 
These are far from elegant, require a second PSU, but interesting nevertheless.
 
This is nice and symmetrical with an ideal CCS...
 

 
...but even with a cascode it's deteriorated a bit.
 

 
What can we try to improve things a bit? Here's what we can get with the IXCP10M90 with CCS loads...
 

 
At 80Vpk-pk, 0.25% THD
 

 
40Vpk-pk, 0.117%
 

 
Now with the DN2540, 170Vpk-pk, 0.07% THD
 
 
 
These are all just simulations, I've got no reason to build any of them. Kept me out of trouble for a couple of hours tho'...
 
w

 

[wdiabc]

Quote:

Tried a lot of variations on this. I found the spice model for IXCP10M90S (strictly speaking a regulator) is just a MOSFET.
 
These are far from elegant, require a second PSU, but interesting nevertheless.
 
This is nice and symmetrical with an ideal CCS...
 

 
...but even with a cascode it's deteriorated a bit.
 

 
What can we try to improve things a bit? Here's what we can get with the IXCP10M90 with CCS loads...
 

 
At 80Vpk-pk, 0.25% THD
 

 
40Vpk-pk, 0.117%
 

 
Now with the DN2540, 170Vpk-pk, 0.07% THD
 
 
 
These are all just simulations, I've got no reason to build any of them. Kept me out of trouble for a couple of hours tho'...
 
w

Hi W,
Can help comment on this circuit? I come up with this last night and did a quick build, it performs very nicely with almost no distortion, yet no feedback is used. 
 

 

[wdiabc]

Q2 and Q3 are bjts that will take inputs, + and - or can be unbalanced 
Output are from the emitters of Q8 and Q9. 
 
This is a SRPP + emitter follower. almost flat down to 30Khz, according to my scope measurement 

 

[wakibaki]

I made R10, R11, 20k, R5 300, D1 1.5V but emitter of Q8, Q9 is ~1.7V.
 
Can you give me some spot voltages?
 
w

 

[wdiabc]

I made R10, R11, 20k, R5 300, D1 1.5V but emitter of Q8, Q9 is ~1.7V.

Can you give me some spot voltages?

w

Sorry. Power supply is 400v. Bias set at 200v. First stage at 1.3ma and the second stage at 3.9ma.

Donny

 

[wakibaki]

 
I have 1.3mA in R9 and 3.9mA in R13, but emitter of Q8 is still only ~2V. Can you see what the problem is?
 
w

 

[jcx]

even if working as intended it has a basic problem - the load is a nearly pure C, the current demand is 90 degrees phase shifted, orthogonal to the resistor/mirror multiplied current
 
the R current adds nothing at the time of C load I demand peaks
 
I thought the Broskie tube cad articles were clear on the "SRPP derived"  impedance multiplier concept
 
nothing like that is going on in this cirucit - nothing is in a place to "sense" the load current - you are just adding a fixed impedance/phase current modulation

 

[wakibaki]

Quote:

I thought the Broskie tube cad articles were clear on the "SRPP derived"  impedance multiplier concept
 

 
Got a link, please, jcx?
 
w
 
OK, found it...

 

[wakibaki]

@jcx OK, I understand what you are saying, if this circuit is truly SRPP then one would expect to see some feedback from the collector of Q5 to the base of Q2. I've been taking the view that I'd allow the poster to to correct the circuit rather than trying to second-guess what his intentions are, or with the presumption that his idea of what constitutes SRPP is conventional.
 
@wdiabc You need to look at the circuit you have posted, check it for errors, and provide some more details, particularly of spot voltages at various points and show exactly how you intend the inputs to be applied and the outputs taken. I also need to know if the values I have chosen for R10 and R11 are in the range you intended. I am simply slavishly copying your circuit into the simulator without thinking too much about how it is intended to function.
 
w 

 

[wdiabc]

Hi W,
the base of Q8 and Q9 shall connect to the upper side of each 150K resistor. 
 
Sorry about the confusion but my schematic was pretty clear about where the base of the Q8 and Q9 shall be connected at. 
 
Let me explain a little about this circuit, this circuit is like a class A "full bridge" driver and the two upper output transistors are driven by the 150K resistor, acting like an emitter follower, the two lower output transistors are connected to the first stage using current mirror, so this circuit becomes a interesting class A push-pull slash emitter follower slash SRPP circuit. 
 
Sorry I was traveling for the past two days was not able to get back to you sooner. 
-D
Quote:

 
I have 1.3mA in R9 and 3.9mA in R13, but emitter of Q8 is still only ~2V. Can you see what the problem is?
 
w