PHP Code:
WARNING:Xst:736 - Found 10-bit latch for signal <v_number$mux0002> created at line 60. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal <v_err$mux0000> created at line 60. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal <v_empty$mux0000> created at line 60. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal <v_full$mux0000> created at line 60. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:647 - Input <clock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <Min59> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ClockUpdate> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:737 - Found 4-bit latch for signal <NextHr10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <NextHr1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <NextMin10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <NextMin1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:1710 - FF/Latch <NextHr10_2> (without init value) has a constant value of 0 in block <clock_out>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <NextHr10_3> (without init value) has a constant value of 0 in block <clock_out>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <CurrHr10_2> (without init value) has a constant value of 0 in block <clock_out>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <CurrHr10_3> (without init value) has a constant value of 0 in block <clock_out>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <NextMin10_3> (without init value) has a constant value of 0 in block <clock_out>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <CurrMin10_3> (without init value) has a constant value of 0 in block <clock_out>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2170 - Unit statemachine : the following signal(s) form a combinatorial loop: v_state<4>, v_full_mux0001, v_state<2>, v_state<6>.
WARNING:Xst:2170 - Unit statemachine : the following signal(s) form a combinatorial loop: v_state<1>.
WARNING:Xst:2170 - Unit statemachine : the following signal(s) form a combinatorial loop: v_state<3>.
WARNING:Xst:2170 - Unit statemachine : the following signal(s) form a combinatorial loop: v_state<2>.
WARNING:Xst:2170 - Unit statemachine : the following signal(s) form a combinatorial loop: v_state<6>.
WARNING:Xst:1710 - FF/Latch <statemachine_1/v_number_mux0002_0> (without init value) has a constant value of 0 in block <top_car_park>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <statemachine_1/v_empty_mux0000> (without init value) has a constant value of 0 in block <top_car_park>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <statemachine_1/v_full_mux0000> (without init value) has a constant value of 0 in block <top_car_park>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <statemachine_1/v_number_mux0002_9> (without init value) has a constant value of 0 in block <top_car_park>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <statemachine_1/v_number_mux0002_8> (without init value) has a constant value of 0 in block <top_car_park>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <statemachine_1/v_number_mux0002_7> (without init value) has a constant value of 0 in block <top_car_park>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <statemachine_1/v_number_mux0002_6> (without init value) has a constant value of 0 in block <top_car_park>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <statemachine_1/v_number_mux0002_5> (without init value) has a constant value of 0 in block <top_car_park>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <statemachine_1/v_number_mux0002_4> (without init value) has a constant value of 0 in block <top_car_park>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <statemachine_1/v_number_mux0002_3> (without init value) has a constant value of 0 in block <top_car_park>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <statemachine_1/v_number_mux0002_2> (without init value) has a constant value of 0 in block <top_car_park>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <statemachine_1/v_number_mux0002_1> (without init value) has a constant value of 0 in block <top_car_park>. This FF/Latch will be trimmed during the optimization process.
those are the warnings i believe that are causing the problem
PHP Code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.Numeric_STD.all;
entity statemachine is
port(
clock : in std_logic;
reset : in std_logic;
in_pin : in std_logic;
out_pin: in std_logic;
empty : out std_logic;
full : out std_logic;
err : out std_logic;
number : out std_logic_vector (9 downto 0)
);
end;
architecture struct of statemachine is
type state is (S_RESET, S_ERROR, S_FULL, S_EMPTY, S_ADD, S_SUB, S_NORMAL);
signal next_state,current_state : state;
begin
--------------------------------
-- RESET PROCEDURE
--------------------------------
zero : process(clock,reset)
begin
if (reset = '1') then
current_state <= S_RESET; --go to RESET state
elsif rising_edge(clock) then
current_state <= next_state;
end if;
end process zero;
------------------------------
-- STATE MACHINE
------------------------------
states : process(in_pin, out_pin)
variable v_state : state;
variable v_err, v_full, v_empty : std_logic;
variable v_number : std_logic_vector(9 downto 0);
begin
case v_state is
when S_RESET =>
v_number := "0000000000"; --reset counter to zerp
v_err := '0'; --error value = 0
v_full := '0'; --full = 0
v_empty := '1'; --empty = 1 as full reset
v_state := S_EMPTY;
when S_EMPTY =>
if (out_pin = '1') then
v_state := S_ERROR;
elsif (in_pin = '1') then
v_number := v_number + 1;
v_state := S_NORMAL;
else null;
end if;
when S_NORMAL =>
v_full := '0';
v_empty := '0';
if (in_pin = '1') then
if (out_pin = '1') then
v_state := S_NORMAL;
else
v_state := S_ADD;
end if;
elsif (out_pin = '1') then
v_state := S_SUB;
else null;
end if;
when S_ERROR =>
v_err := '1';
v_state := S_ERROR;
when S_FULL =>
if (in_pin = '1') then
v_state := S_ERROR;
elsif (out_pin = '1') then
v_number := v_number - 1;
v_state := S_NORMAL;
else null;
end if;
when S_ADD =>
if (v_number = "1111111110") then
v_number := "1111111111";
v_full := '1';
v_state := S_FULL;
else
v_number := v_number + 1;
v_state := S_NORMAL;
end if;
when S_SUB =>
if (v_number = "0000000001") then
v_number := "0000000000";
v_empty := '1';
v_state := S_EMPTY;
else
v_number := v_number - 1;
v_state := S_NORMAL;
end if;
when others => null;
end case;
next_state <= v_state;
err <= v_err;
full <= v_full;
empty <= v_empty;
number <= v_number;
end process;
end struct;
And that'd be the code
I'm baffled as my 24hr clock component works perfectly!
