Another Beginning Eagle Question: SMD to ground plane
Mar 24, 2006 at 11:27 PM Post #2 of 11

kin0kin

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how did u connect the points? when using smd, you need to use the "route" tool to connect them, if you used the normal "wire" tool...it doesnt work..it will treat them as not connected although the wire tool works with TH components.
 
Mar 24, 2006 at 11:38 PM Post #4 of 11

tangent

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Quote:

Originally Posted by dsavitsk
I added small via's


That may be the problem. You don't normally add vias manually. You just click while routing to put a kink in the trace, then mouse up to the tool bar at the top of the screen -- you'll be dragging a trace along while you do this, but just ignore it -- and change to the other layer, then continue routing. As soon as you change layers, EAGLE automatically adds the necessary via.
 
Mar 24, 2006 at 11:55 PM Post #5 of 11

dsavitsk

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Hmmm. No luck. I select the routing tool, click on the starting point on the component, draw a short route into space, click, select "bottom" from the dropdown, go back and click on the ground plane, and the douting operation stops, but no via appears and the short drawn route is still connected to the other components via air wires. Have I set somethig wrong? The through hole components seem to be connecting okay.
 
Mar 25, 2006 at 6:39 AM Post #6 of 11

tangent

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Is the ground plane a named polygon, or something else?

Can you post a sample board so we can see what you're working with?
 
Mar 25, 2006 at 7:01 AM Post #7 of 11

kin0kin

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testing.jpg

did a little test, works for me....you might wanna redraw that ground plane..sometimes the polygon doesnt work properly for some reasosn.
 
Mar 25, 2006 at 7:42 AM Post #8 of 11

dsavitsk

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I got it to work, but what I had to do was click the component, draw a route into space, switch to bottom, then draw the route to a grounded leg of a through hole component. When I open up a board file, the polygons are not filled in and there are traces all over the ground. When I push rats nest, the ground plane fills and everything looks okay. If this is not how it should be, then I'll post a file.

A second question, when I run "DRC;" the lst of errors is extensive. Some of them are things that don't seem much like errors -- like the outlines of SMD resistors touching even though the pads have plenty of space. Can I ignore these, or is there a way to make them go away (other than adding more space?)
 
Mar 25, 2006 at 7:51 AM Post #9 of 11

DaKi][er

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You’ll be able to rip up the ground trace mess afterwards to clean it up, you should just be left with the top layer trace terminating at the via to ground and that is it

You'll also have to setup your DRC clearances as well, the one you mention is the spacing between SMD pads and other pads of the same signal, the default is 8mil and you can safely set that to 0 as long as you know you have room for them
 
Mar 25, 2006 at 4:47 PM Post #10 of 11

tangent

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Quote:

Originally Posted by dsavitsk
When I open up a board file, the polygons are not filled in and there are traces all over the ground. When I push rats nest, the ground plane fills and everything looks okay.


That's normal.

Quote:

when I run "DRC;" the lst of errors is extensive.


My advice is to set the design rules according to your board house's manufacturing limits. Sometimes I will use even stricter limits, such as setting the minimum trace width to something higher than the default of 8 mils (?) so I can get a better price on boards. Board houses often charge more for fine-pitch trace work.

I advise against relaxing the DRC limits until the errors go away, even if you decide the errors you have now are harmless. It may be that in the future, you make what EAGLE considers to be the same class of error as one of those you disabled, but you would personally not consider them the same.

Quote:

Some of them are things that don't seem much like errors -- like the outlines of SMD resistors touching even though the pads have plenty of space.


You're not thinking about manufacturability. What do you suppose happens to the solder when you tin one of those pads? The solder doesn't know it's not one big pad, so it flows over both of them. Maybe you don't care in that particular instance, but what the DRC limits are trying to do here is point out that you don't have any solder mask between pads.

I'll give you an example from the PINT: there's a via between one of the op-amp pins and a bypass cap hanging off of that pin. When you apply solder to the op-amp pad, the solder also flows across that via and onto the cap pad. This gave me two DRC errors (one for the via touching each pad) and I chose to ignore them, because I knew it would be populated by hand. If these were machine assembled, that could cause problems.

In the end, I had 6 DRC errors on the PINT that I chose to ignore. Every time I ran DRC, I first checked whether there were more than 6 errors. If not, then I'd just say "Del All". But frequently during development, I'd make some mistake and the DRC error list would be longer, and I'd have to do some fixing to get the error list back down to those few I was comfortable with. If I had relaxed the DRC limits to get rid of the 6 I chose to ignore, I would have missed some that I would have wanted to fix, if I had known about them.
 
Mar 25, 2006 at 6:55 PM Post #11 of 11

guzzler

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To get a via to work manually, draw your trace to it from your component, and then simply name the trace the same as the ground polygon. The polygon will adjust automatically.

The other thing to consider with SMD pads is they don't connect automatically to a drawn trace like a through hole component. You need to draw a Signal between your two pads, and then name the trace the same as the signal. This is the case if your SMD pads have a "Clearance" error and the cross hatching looks like a trace into the pad
 

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