Garbz
Headphoneus Supremus
- Joined
- May 19, 2004
- Posts
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- 14
Who needs weekends
I went ahead and tried it. No sucess. Just so you know what i'm trying to do. I'm using a 74HC74 D type flipflop. The clock from the clock source, and the Data from the S/PDIF line. The output Q should have only the jitter inherent in the clock itself. This is what common reclocking circuits do.
There is a clock signal on that pin but whatever it is it's not the correct S/PDIF frequency. I'm not going to rule out that I've burnt out the flipflop with constant resoldering, or that I've set up something incorrectly but I will experiment further. Thistime on the weekend
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Could you do me a favor since I don't actually have a frequency counter or ocilliscope (which would eliminate the guess work). Could you please check the frequency output of the S/PDIF signal? R5 on the schematic or Pin 5 from bottom left. in Bryan's pic.
There is a clock signal on that pin but whatever it is it's not the correct S/PDIF frequency. I'm not going to rule out that I've burnt out the flipflop with constant resoldering, or that I've set up something incorrectly but I will experiment further. Thistime on the weekend
Could you do me a favor since I don't actually have a frequency counter or ocilliscope (which would eliminate the guess work). Could you please check the frequency output of the S/PDIF signal? R5 on the schematic or Pin 5 from bottom left. in Bryan's pic.