[jcx]

you are free to put the little gnd triangle on any (one) node in a circuit and it will (except in sims with the flawed macromodel issue) behave exactly the same - all "V" readings in a real circuit are V difference readings - and you can choose your reference in any way that aids understanding

a convenient location for the Spice node 0 gnd symbol in active supply split circuits is the output of the supply splitter

in LtSpice you can make difference measurements explicit by holding down the button when selecting a circuit node for display and draging the probe to any node you wish to use as reference - the probe symbol will change from red to black and select the reference node when you release the button - the trace in the waveform viewer will have a label like: V(n003,n007) indicating it is an explicit difference; the reference is not displayed when it is referenced to Spice node 0 = gnd

 

[PJPro]

Finally started getting some waves coming out of LTSPice......with a slight backward step in that it's only a CMoy with rail splitter. But useful, nonetheless, to allow me to get my head around the tool.

 

[PJPro]

Have returned to this project after a month of inactivity

Made quite a bit of progress. I've placed the whole circuit into LTSpice and have tweaked the values of the components based on the "quality" of the square wave coming out of the simulation.

Question. Has anyone successfully simulated an active ground design eg M3? For some reason LTSPice complains about a singular network when I try to link the left and ground channels through a 32R load, representing a headphone. It identifies issues with the buffers on the left and ground as the problem.

 

[PJPro]

OK. I have modelled a single, complete channel of an M3 using LT Spice. (I have ignored the complications around the active ground). Has anyone tried this?

I've sent a square wave through the circuit using the following values PULSE(-10m 10m 0 0 0 .0000002 .0000004) where the parameters are PULSE(V1 V2 Tdelay Trise Tfall Ton Tperiod). The simulation runs for .0000008s.

The results are far from what I was expecting. The square wave has gone, to be replaced by something looking more like a sine wave.

Is it reasonable to expect the M3 to be able to cope with a wave as fast as the one specified above? If not, can you suggest more reasonable parameters? Or does this simply demonstrate the limitations of modelling?

 

[PJPro]

I am still progressing this project and am documenting the design process here.
 
I stumbled across an application note for the BUF634 on the Texas Instruments website, written by Burr-Brown. It's called "Combining an amplifier with the BUF634". You can find the application note here.
 
The application note held some tweaks which I've incorporated into my design. However, it seems that they have made a mistake. The polarised caps on the opamp rails (fig 2) seem to be the wrong way round. I would have expected the negative leg of the cap to be attached to the negative rail and vice-versa for the positive rail.
 
Can someone confirm this for me please?

 

[PJPro]

Incidentally, if my design thread is cobblers I'd be grateful for corrections

 

[MisterX]

 They're right.
 V- has more negative potential then "ground" so the positive lead connects to "ground".
Quote:

 The polarised caps on the opamp rails (fig 2) seem to be the wrong way round. I would have expected the negative leg of the cap to be attached to the negative rail and vice-versa for the positive rail.

 

[PJPro]

Thanks for your reply MisterX. 
 
I got a bit confused there as your statement mirrored mine...so how could they be right? 
 
Refering back to the original application note, they do indeed have the negative leg of the cap attached to the negative rail, as I would expect.  I must have misread the schematic. 

 
I'll update my design thread.

 

[PJPro]

This is the design so far. 
 

 
It's getting more complex than I would have liked and is likely to cost more than I expected.  Anyone spot any silly mistakes? 
 
I think the design has a little way to go yet.  Clearly, I still need to consider the power circuit and I may have to look at ways at reducing the cost of the components.
 
Any comments gratefully received.

 

[Pageygeeza]

I'm getting really interested by this project.  I've wanted to design my own, but admittedly I don't think my heart is in it.  
 
How are you going to set your amp with this design, will you be using three of the exact same circuits for L/R and ground?
 

 

[Leny]

I’ve not read all of the thread, so here is a quick comment based upon the scheme in post #99.
 
R1 acts with R2 as a voltage divider to cut the signal by 50%. Why cut the signal in an amplifier? It would seem reasonable to ditch R1 and reduce the gain of the amp to compensate. i.e. reduce gain from 3.7 to 1.85. (OPA627 is stable at low gain). (Or maybe R1, R2 simply represents the half-way point of a 50K pot?).
 
Why R3? It’s another (yet tiny this time) voltage divider. Or perhaps you intend to use it in combination with a small capacitor across R4 to limit input bandwidth?
 
I know external biasing of the output of the op-amp can work. However, if you want to get ultra-picky about it consider that according to the Burr-Brown datasheet the negative half of the output has slightly better Power Supply Rejection, hence biasing the op-amp to the positive rail, and hence using the negative output transistor, should bring a theoretical (though small) improvement. (In reality it might not be noticeable). If you do decide to try it then just slide the CCS upwards... top of R11 to positive rail, bottom of R10 to OPA627 output.
 
I don't know about your CCS values, but you might want to try varying the CCS current a tad (via R10) to see if it helps.
 
Reference:
http://focus.ti.com/lit/ds/symlink/opa627.pdf
 
Good luck with it,
L.

 

[Leny]

I just realised that with R3 you are attempting to balance input impedances to the + and - inputs of the op-amp.
 
That is necessary mainly with BJT input op-amps that pull input current. i.e. equal current through equal impedances leads to equal voltages; they cancel and hence there is no DC output offset. This is a DC function, not AC. You have blocked DC to R3 via C1 so it has no effect. Also, the 560K would be a party pooper if you were really keen to balance impedances.
 
(Note for future, especially if you ever choose a BJT input op-amp; R4 provides input AC load and DC bias path, which is why choosing a value is a compromise).
 
However, here you actually have a FET input op-amp with tiny, tiny input current requirements. As such balancing the impedances is less of an issue.
 
Conclusion: delete R3 !
 

 

[Ant1Xr1st]

Put 1-4.7ohm after each BUF634
Put 22-100om between OPA627 and BUF634
C4/C2 are not needed - use big electrolytic 470-2200u

 

[Avro_Arrow]

It looks like you are trying to build a PIMETA V1
You should read through the article for design tips.

 

[Avro_Arrow]

FET input amps need to have balanced input impedances too, but for a different reason...it is because of the capacitance
of the FETs. R3 should equal the impedance seen by the - input, including any multi-loop resistors. Articles by Walt Jung
explain all this in more detail.
 
Quote:

I just realised that with R3 you are attempting to balance input impedances to the + and - inputs of the op-amp.
 
That is necessary mainly with BJT input op-amps that pull input current. i.e. equal current through equal impedances leads to equal voltages; they cancel and hence there is no DC output offset. This is a DC function, not AC. You have blocked DC to R3 via C1 so it has no effect. Also, the 560K would be a party pooper if you were really keen to balance impedances.
 
(Note for future, especially if you ever choose a BJT input op-amp; R4 provides input AC load and DC bias path, which is why choosing a value is a compromise).
 
However, here you actually have a FET input op-amp with tiny, tiny input current requirements. As such balancing the impedances is less of an issue.
 
Conclusion: delete R3 !