OK, still a few things, and a bit of confusion.
Don't rotate the 1543. The idea was to get pins 1,2,3 right next to the 2707. Especially to get the bit clock trace as short as possible, and to avoid running the trace over any cuts in the ground plane. All else should subservient to these goals.
So, we can gain some space, and make some changes.
You could tweak the crystal oscillator layout a bit. There is no need to have the bypass capacitors share a via to ground. Split them apart and put them either side of the crystal. This will allow you to move the 2707 to the right a bit, which may make life a bit easier, but might not be worth the effort.
You have swapped the inputs to the DAC, somehow pins 1 (bit clock) and 2 (word select) have been swapped since your last layout. This will cause problems
And has made the layout harder.
But, move the 1543 back over the 2707, and rotate it 90 degrees left to get the input pins as close to the 2707 as you can. Now we need to work on removing those cuts in the ground-plane. They are critical. Get the power from the left side of the chip not the right (except for the run to the pull up for DT which stays as it is.). The series resistors for the USB inputs can be moved so that they jump the power trace. (You may need to jump the USB to the ground-plane to jump one trace, but this is OK, especially if you do it well away from the 2707.) You can now remove all of the cuts in the ground-plane. If you are happy to run the data line thought a corner, take it through the top right corner, where it will run next to the other DAC inputs. You can punch the via to ground for pin 24 on the other side of the pin to make room.
You have the AGNDR and PGND sharing the same via to ground. Bad. In particular we want the PGND to go to the ground-plane with minimum distance. Vias have some inductance, and sharing the via with AGNDR means we may get some interference. You must split these onto separate vias. Integrity of the PLL power is paramount. Similarly, pins 25 and 26 should have individual vias to ground and not share traces.
The trace to HOST from USB power could be moved about. There is no reason to put the pull down resistor in a row with the other resistors. You have the entire trace gratuitously looped upward for no reason other than to put the resistors in a line. This further squashes things to the left needlessly, and has pulled the cut in the ground-plane under the 2707 where we really don't want it. With pins 1 and 31 no longer connected together, if you use vias on the outside of pins 1 and 31 you have room to slip the HOST trace out with no further ado. Putting the via on the outside of pin 1 is OK, even good, as it gets it right next to the other side of the de-coupling capacitor for the power input for that functional unit. Pin 31 couldn't care where its via is as we are not using the headphone amp in the chip.
A remaining possibility involves a small change to the schematic. Placing small inductors in series to control the rise time of the three DAC digital inputs. This technique is well accepted and seems to yield good results. Also, placing ferrites in series with the various +V pins on the 2707 can help to reduce local cross coupling. Although you are not using the DAC in the 2707, protecting the PLL, and keeping noise off the digital outputs remains crucial.