For easier comparison, 1uV on Terminator (4.6V xlr) roughly corresponds to 133dB.

Desoldering of delicate IC like 1704 need strict control of temperature and heating duration, and even if it functions normally after the whole process it still could experience performance degradation due to thermal stress it went through. So I understand why Kingwa won't do it. As to the...

Since I fixed the digital board last year, this is the only left major complaint I have with my M11. I've long been suspicious its related to analogue boards, thanks for verify it for me. Four months ago I shoot Kingwa an email asking the possibility of providing a "push-pull output stage...

O.K. I'll try to clarify things a little with a picture: (1) Why only BCLK matters: please refer to PCM1704 datasheet page 7 & FIGURE 1. --- "The change in the output of the DAC occurs at the rising edge of the 2nd BCLK after the falling edge of WCLK." (2) BCLK* output from DSP is generated...

Not exactly. If you only want a taste of what it might bring to the table sonical-wise, the minimal mod will involve cutting one end of impedance-matching resistor (of BCLK) to PCM1704s and wires it directly to DDC output. Theory behind the mod: After study the datasheet of PCM1704 and I2S...

Actually there is another upgrade path if you (1) only use I2S input (2) only use NOS mode (or upsampling using computer) (3) Have necessary DIY skill --- you can (almost completely) bypass DSP chip and use your low jitter DDC with I2S output to drive PCM1704s directly. This is the lowest...

If you check the design, BNC input is routed to BB DIR9001 which can only handle up to 108k. All other inputs are routed to Wolfson WM8805 which can handle 192k. DIR9001 has better performance than WM8805 but lower input rate.

I see, so you are referring to the "Reconstruction filter (post filter)" and it is implemented as 1st order analog filter, and both NOS and Master dacs have it since they share the same analog circuit boards. (Sorry I misinterpret your NOS dacs web pages, it kind of give me the impression the...

Thanks for the explanation, that clarify things a lot.   One more question: Is the 6dB/oct filter implemented in hardware or DSP-1 processor?

Nice job.   The one marked LEJ#0Z is ADP150; the other two marked "L337" are generic 3.3V LDO --- can't locate the brand. I replaced both with ADP150s.

Hi Kingwa,   Can you explain a little bit about the new Nos mode. Figure every one in this forum will very much like to know.

Thanks for this information.

Yes, you're right.   So next time I mention BYPASS option, I should add "Try at your own risk!!". Since Kingwa never warn me of any adverse effect, figure at least it won't burn your DAC. --- I've used this setting for couple of  months and also have the 98.3Mhz TCXO removed from my DAC.

In I2S spec. there are three mandatory signals:   WCLK (word clock, or left right clock (LRCLK)) - 44.1k, 48k, 88.2k, etc. BCLK (bit clock) - usually WCLK x 2 x 32 in most implementation DATA (data) - include left and right channel data   MCLK (master clock) is optional, it is usually used...

My is a NOS11, never has a M11 for comparison so can't say for sure. My guess is yes, both will work and sound similarly in BYPASS mode with one difference: M7 can only handle input up to 192k and NOS7 with new improved implementation can handle up to 384k. That could translate to less gates...

  In a traditional NOS implementation, the signal should be "bit perfect" transferred to the DAC chips, no oversampling involved, no alternation of any kind. AGD's implementation is more unconventional, though not oversampled but the input signal will be altered by low pass filter no matter in...

No. It will reclock using internal 98.3MHz XO.   The only benefit you get by connecting a SU1 or F1 to NOS7 is galvanic isolation. The SQ improvement is limited compared to if it's connected to a Master7. The only way as far as I know of for you to enjoy the SQ improvement as observed in...

Yes.

PLL - Phase locked loop.   The dsp chip on M11 have two PLL built inside, it can be used to reshape input clock (to reduce jitter). But in your case, this will actually increase jitter - SU-1 have much better clock.   Refer to "http://www.audio-gd.com/Master/Master-11/M11EN_Use.htm" ---...

Good job!   Just remember to disable PLL. Also expect minimal 100 hours burn-in time.

It has only one chip "Quadruple differential Line Receiver" on it and consume less than 15mA according to AGD's spec, so only minimal noise will be generated.

  A partial crop; make it more clear. Or you can consider the three 1 ohm resistors at bottom of the picture.

Yes, it is connected to Amanero's 3.3V. But I don't think you can properly solder a wire to it without collateral damage.   There are two 3.3V rail in Master 11, marked P1 & P2 in the picture below, the more readily accessed P1 (same as Amanero's 3.3V) are the bottom end of 1 ohm resistors at...

The pin out for the 7 pin connector is: (top to bottom) LRCK (word clock) DA (data) BCK (bit clock) MCK (master clock) NC GND V3.3   For the 5 pin connector: DATA (data) BCK (bit clock) WCK (word clock) MCK (master clock) GND   Also I'll suggest using a jst xh female connector...

Yes, from CCHD-575's spec, it doesn't have enable pin and the list typical consumption is 15mA. Since on my unit the measured current draw is 14mA for the XOs so only one is running while working and on Singxer's website, it mention "Customized CRYSTEK femto clocks are used". So maybe the...