This is BIG. Most ESS solutions are happy to use the ASRC and its accompanying PLL for jitter reduction. BUT... if you can use a buffer and re-clock the audio after the I2S output of the USB chip with an excellent clock, and use an identical clock as master for the ESS ASRC system, THE ASRC will act synchronously, as long as the clocks and accompanying jitter stay identical or within tolerance.
Not that letting the anti-jitter system as built into the chip isn't great... it does a KILLER job of eliminating any jitter left remaining on the audio clock output from the Asych. USB receiver. But in my book, extra isolation with a buffer, and cleaning up the input signal to the point little to no jitter reduction is required (and less DSP on the signal) is a good thing.
I may be incorrect, but I think the late Charlie Hansen was a proponent of this way. And others.