[holland]

all the little traces with Q1, Q2, Q3, D1 and D6 can be moved top side.  If you reroute the topside trace between C1 and Q1 and C3.  Move the trace between C1 and Q1 going up along the edge after C1, and move the trace from C3 to Q1 lower between Q3/Q2 and Q1, which should shorten the trace between the + rail and Q3 as well.
 
I'm also wondering if the ground plane should be cut between C3 and D2 using a smaller trace for ground between those 2.  I'm not sure, if the dirtiest ground is between C3 and D2, possibly restricting contamination may be beneficial.  I'm no expert though.
 
BTW, there's more room, would you reconsider a common mode choke now that a SOIC package was introduced.

  A small film cap on the AC input too?
 
Edit: also curious why the AC input traces are alternating sides?

 

[rds]

 
 Yeah, it looks like all traces save maybe one could be moved topside and you'd have a near ideal ground plane.

    Quote:

all the little traces with Q1, Q2, Q3, D1 and D6 can be moved top side.  If ...
 

 

[tangent]

Quote:

How thick are you talking about?  The thin traces are 15mil and the thick ones are 50mil.

 
I like to get signal traces up to 40-50 mil if I can manage it on a given layout. That works well with standard 0.1" pin spacing components. Down around your SO-8 chip you'll have to neck things down a bit.
 
As for the power traces, I design those heuristically. There is no one rule, and the rules I use often conflict so I have to balance them against each other. The ones that come immediately to mind are:
 
- Prefer running major power and ground signals as planes rather than traces
 
- When using traces instead, pick a size as large as possible on your board. Consider it the "bus width" in that particular design. There are a few such in the YJPS, for instance, over 100 mil. 150 maybe? That's probably too much for a board this compact. The point is, pick a size and stick to it. Use it only for those connections that can't be readily made with a plane, such as connecting two planes together.
 
- AC side should be kept from DC side by at least 8mm. Use your CAD package's DRC rules to enforce this.
 
- Keep space between unregulated and regulated DC sides.
 
- Keep space around pads. Your board maker might be capable of 6/6 spacing, but that doesn't mean you need to push it that hard. I like to use more like 12-20 mil.
 
- Use relatively thin trace widths for pours; 8-12 mll. This heuristic and the previous one combine to ensure that fenestrations do indeed improve solderability. Your current fenestrations are scarcely better than doing without because the four connections are so thick and the spacing so tight. That turns the plane into a big heat sink, increasing joint creation time and increasing the risk of cold joints and damaged components.
 
 
Quote:

what traces on what layers?

 
The first choice to make is whether you put the planes on the outer layers and the signals inside, or vice versa. The first choice is better for RF immunity and low-noise performance, while the second is better for DIY hackability. Another thing to consider is that the outer layers will have thicker copper. This tends to argue for putting the planes inside since they make up for thickness with area; let the outer layers get the benefit of thicker copper on the relatively thin traces.
 
You probably want two layers dedicated to signals, one the primary signal layer, the other the "I need to jump this signal over that other one" layer. You use these like in 2-layer design.
 
The other two layers are for planes. In old-school digital design, it was easy: one is +5V and the other GND. For this design, maybe they are unregulated ground and regulator ground instead. There should be no need for a +V plane, since the connection from the pass transistor emitter to the VOUT connector should be very short.
 
Speaking of, that do-si-do you've got going on around Q1 bugs me. If you're set on the Q1 part, you can fix it by mirroring the design top-to-bottom so the Q1 emitter is on the left, and can thus be a tiny jump to the VOUT connector. An alternative would be to seek out a transistor with a different pinout to achieve the same end.
 
Getting back to planes, you should split up your current single big plane. You don't want such a ready coupling path between the noisy AC and DC output sides, and probably want to segregate unreg and reg DC from each other, too. I would set up three grounds: UGND, CGND, and RGND. UGND is the unregulated ground, and connects all the grounds on the unregulated side of the board. CGND is the control ground; that is, for connections in the regulator proper. RGND is the regulated output ground, composed only of the GND pin on the VOUT connector and the output cap's ground. Each of these connects to its neighbor with a short, fat trace. Think of the separate planes as pools for current to swirl around in, not bothering the next pool down the line connected via a small stream.
 
As for how this maps to layers, I'm actually having trouble justifying a fourth layer, but you're going to get it for free... All you need is one more layer for the two or three segregated ground planes. You don't want to put them on different planes because you're trying to avoid creating a coupling path. Maybe you just create a mirrored pair of each plane, to lower the overall impedance.

 

[00940]

The design with the groundplane is somehow a step backward as it is now.
 
Get rid of the ground plane for the power section. It's not really needed. Big fat tracks (power and ground on different layers and overlapping if possible) are more than good enough. Only keep a true groundplane for the interior of the blue square.
 
You don't want a groundplane under the input pins of your opamp. You should move around the decoupling cap too, so that the pads aren't there either.
 
The decoupling cap of the opamp could play tricks on the stability of the regulator btw; consider adding a small R in serie.
 
On the tracks around the pass transistor, I'd at least put the output track on top of the board and the input one under the transistor. Less crossing that way.
 
p
 
 
 
 
 
Here is the layout (except the top groundplane that was only shielding) on which Jung achieved outstanding performances.... just food for thought. Another point to consider before deciding how many layers to use is that you don't want to jump too quickly to production and you will need to do some testing. Prototyping runs with 4layers don't come cheap.
 

 

[cobaltmute]

Ok, Ok, I have learned my lesson - do not post a PCB design without taking a good look at.  I "poured and went".  Should have spent more time analyzing, but I was tired and was about to go to sleep.
 
I'm working on a new, not ground plane layout, based on some of tangent's comments.  Should be easy to show with a ground plane as well.
 
I'll post soon.

 

[cobaltmute]

Rev 0.15


- Changed the CCS to a LED/BJT based one.  Why?  Went back and read the Jung article on CCSes.  The cascoded JFET is very good, but it needs lots of voltage to get that performance.  We're not likely to always have that, so it seemed that the LED/BJT would be better.
- flipped the layout to straighten out routing around the pass transistor
- bumped out some trace sizing.


No, I haven't written off the request of the SMD choke, just focusing on other items at the moment.


Schematic




Board:



Still need put a footprint in for 5.08mm screw terminals for the AC input, although 2.54mm terminals should fit.


I'm also still looking at the ground plane.  I see the point of the screen that Jung/Didden did in the article referenced by 00940, but that was on a single layer design where the plane was only attached in one point to the circuit.  I don't have a good place to do that, but I can see that as a very valid item to do in going to four layers - one layer for the error amp circuits, one layer screen, and the other two layers split as ground.

 

 

[tangent]

Regarding the ground plane, I think you should put it back, enclosing just the regulator proper: from the board's top, right, and bottom edges to Q2 on the left. Then cut a hole around the op-amp.
 
I'd increase the ground trace width between D2 pin 4 to just past the positive C3 pin as it nears the board edge. 100 mil at least.
 
The schematic part labeled TPG1 is TP2 on the board?
 
It may be an artifact of the imaging, but I don't see a via between the green op-amp pin 4 trace and the red tree ground. Is it missing, or just blown out in the picture?
 
You might add a "+" silkscreen near the LED anodes. You can either modify the current footprints or just add text to the board. The current markings will be hard to discern once printed.
 
I'd add some snubber caps around the bridge. Since you're already specing SMT caps for the op-amp, they'd work here, too.
 
I don't see a reason for Q4. A resistor will work just fine, given that we have extreme confidence in our regulator, yes? That is, unless you were planning on making this a fully-adjustable supply with VR1, which I argue against below. With adjustment of a few volts for trimming, you don't need a separate CCS here.
 
The same argument for Q5 is a lot harder to make. For one, it's not merely a LED current limiter. For another, the reference voltage accuracy directly affects the regulator accuracy; indeed, errors are multiplied by the op-amp gain.
 
You want at least one resistor inline with VR1, maybe 2. Using a pot alone for gain adjustment will give too wide a range. You want a relatively small pot value here, with most of the feedback resistance in fixed resistors.
 
I'd add an unregulated DC test point. Very useful in testing and debugging.
 
Is the D2 footprint big enough? I would think a 1 or 2 A bridge would be wider than that. You've got enough room around it now for the size I'd expect, but you want the silkscreen outline to reserve all the space the part actually needs so you don't mess up and push something too close later.
 
Q4 should rotate right 90°.

 

[cobaltmute]

 
Quote:

Regarding the ground plane, I think you should put it back, enclosing just the regulator proper: from the board's top, right, and bottom edges to Q2 on the left. Then cut a hole around the op-amp.
 
I'd increase the ground trace width between D2 pin 4 to just past the positive C3 pin as it nears the board edge. 100 mil at least.

 
Next revision will have a ground plane, and we can discuss what how it is setup when I post.
Quote:

 
The schematic part labeled TPG1 is TP2 on the board?
 
It may be an artifact of the imaging, but I don't see a via between the green op-amp pin 4 trace and the red tree ground. Is it missing, or just blown out in the picture?

There is a via there, and yes, small label difference on the part - I'll fix that
Quote:

 
You might add a "+" silkscreen near the LED anodes. You can either modify the current footprints or just add text to the board. The current markings will be hard to discern once printed.

Take a look here at the grubDAC board - http://diyforums.org/GrubDAC/GrubDACboard.php.  The C pretty clearly marks the cathode, so I don't see a point in changing the silkscreen.  And we've seen no complaints from the grubDAC builders.
 
Quote:

 
I'd add some snubber caps around the bridge. Since you're already specing SMT caps for the op-amp, they'd work here, too.
 

 
I'll have to check space after I fix the bridge footprint (as noted below)
 
Quote:

I don't see a reason for Q4. A resistor will work just fine, given that we have extreme confidence in our regulator, yes? That is, unless you were planning on making this a fully-adjustable supply with VR1, which I argue against below. With adjustment of a few volts for trimming, you don't need a separate CCS here.

 
On the original layout Q4 made sense, as it was taking as much space as a resistor mounted vertical.  Now I've got space, so I'll put it as a resistor since it seems to offend.
 
Quote:

 
The same argument for Q5 is a lot harder to make. For one, it's not merely a LED current limiter. For another, the reference voltage accuracy directly affects the regulator accuracy; indeed, errors are multiplied by the op-amp gain.

 
Agreed and this will stay as is.
 
Quote:

 
You want at least one resistor inline with VR1, maybe 2. Using a pot alone for gain adjustment will give too wide a range. You want a relatively small pot value here, with most of the feedback resistance in fixed resistors.

 
I put in VR1 for adjustment, but I was never really sure about it.  I'm going to put it back to two resistor with no trim.  If you need an adjustable supply, you can socket your resistors.  Convenience or low noise is the way that I see the choice.
 
I think part of this is the BOM as well - given that the noise is a result of referenence noise * gain, lower gain equals lower noise.  The best way to handle this is to spec parts based upon the desired output levels.  Easy enough to setup a spreadsheet with the parts choice for various output voltages (sort of like they did for this regulator: http://circulator.bravehost.com/Gminireg.htm )
 
Quote:

 
I'd add an unregulated DC test point. Very useful in testing and debugging.
 

 
Should be easy enough to add.
Quote:

Is the D2 footprint big enough? I would think a 1 or 2 A bridge would be wider than that. You've got enough room around it now for the size I'd expect, but you want the silkscreen outline to reserve all the space the part actually needs so you don't mess up and push something too close later.
 

 
Well, on check, you happen to be right.  Second time Multisim/Ultiboard has had a screwed up footprint in the master library.  And it is not just the outline - pin spacing is messed up too.
 
I'll fix, re-layout and see what I can do about adding the bypass caps.
 
Quote:

Q4 should rotate right 90°.

 
No need to do so if I change it to a resistor.
 
 

 

[00940]

I'd be curious to have measurements of a regulator with and without a jfet for Q5. Walt Jung didn't bother and all the guys who did PCBs didn't either (including Tangent at the time). But as you said, it's easy to fit a resistor in a jfet footprint.
 
I'll wait for the final layout with groundplane for comments, Tangent nailed down all the problems I saw. 
 
edit: I forgot that decoupling cap: seriously consider a resistor in serie with it. When I simulated a regulator in LTspice, I had serious oscillations if I had a "perfect" cap on the output.

 

[cobaltmute]

Quote:

I'd be curious to have measurements of a regulator with and without a jfet for Q5. Walt Jung didn't bother and all the guys who did PCBs didn't either (including Tangent at the time). But as you said, it's easy to fit a resistor in a jfet footprint.

I should note that the part on the schematic shows a JFET, but that is not was it going there.  The part that is going there has the same pinout so it works as an excellent substitute.
 

 

[cobaltmute]

Rev 0.16 for your scrutiny
 
Changes:
- Q4 has been replaced by a resistor
- Changed the test point naming and added an Unregulated test point.
- Added a larger footprint option for the reference filter cap (noted on the schematic as C7).  This is needed to use 5mm LS caps.
- Switched back to using 2 resistors instead of a trimpot for the feedback section.  I feel that this is more in line with the performance aspect of the regulator - you build it for a specific purpose.  You can always put the resistors in sockets if you want to build and adjustable regulator
- Added bottom side ground plane.
- Fixed the bridge footprint
 
Still to do:
- bypass caps on the bridge
- screw terminals for the AC input
- need to check space around Q1 to ensure a heatsink could sit over the board.  I believe it is close, it may just need to pushed right a touch.
 
About the ground plane:
There are two cuts in the plane to "break" it into three sections, Unregulated, Control and Reference.  The Unregulated section is for the bridge, the control section is for the bootstrap and the op-amp, and the reference section is for the voltage reference and the feedback loop.  I especially felt that it was important to not mix the reference section with the other sections.  Hopefully this layout works.
 
I'd like the think that the PCB is getting very close to the time where a small test run should be made.  A baseline of its performance needs to be taken before trying to tweak it further.
 
Schematic:

 
PCB:

 
And so it is more visible, bottom copper only:

 
 
 

 

[00940]

It's  getting there indeed I think but:
 
- The ground lead of Q2 should rather return to the unregulated groundplane (C3 groundlead) to keep the loop small and logical.
- Your center groundplane can cover most of the opamp, just keep at bay from the input pins.
- On the other hand, I would remove a strip from the center groundplane, removing it from under led2, Q2 and cutting it closer to the leftmost pins of led1, R7. Those components don't need it there and it would create a bigger gap in between the groundplane and the AC entry. If you tombstone R7, you can push led1 to the right a lot and increase the gap even further.
- You shouldn't have a groundplane under the AC entry point and the diode bridge. It can only couple noise and do no good. At least cut away the bit around the ac entry and around the AC pins of the bridge.
- I would bring R5, R6 closer to the opamp pin: flip C4 by 90° clockwise and they can go down a bit.
 
Edit: I think you have room to implement remote sensing. You have to see if you want that feature or not. If you do, you have to link both the power supply and the ground to the sensing section by jumpers.

 

[cobaltmute]

Quote:

It's  getting there indeed I think but:

 
Getting there also means that I need more explanations.  We're starting to get to the optimization stage and optimization without baseline is meaningless. 
Quote:

 
- The ground lead of Q2 should rather return to the unregulated groundplane (C3 groundlead) to keep the loop small and logical.

 
Looking at the both tangents and Jung's work, it seems that this path on the regulator goes to the the Control ground or directly to the central "star" ground.  There is small and logical versus putting the ground of this reference path to a noisier area of the board.
 
Do you have any examples to show what kind of difference we could get by doing this?
 
Quote:

- Your center groundplane can cover most of the opamp, just keep at bay from the input pins.

 
Everything I've read about ground plane and op-amps suggests to remove it around the whole op-amp.  Now we are talking about slower op-amps for this purpose and the output has a very short trace to the first R, and we should benefit from the screen effect, while not affecting the op-amp too much, so I'll do this.
 
Quote:

- On the other hand, I would remove a strip from the center groundplane, removing it from under led2, Q2 and cutting it closer to the leftmost pins of led1, R7. Those components don't need it there and it would create a bigger gap in between the groundplane and the AC entry. If you tombstone R7, you can push led1 to the right a lot and increase the gap even further.

I'm going to make some further cuts/layout changes to increase the gaps, but on a small board it is tough.
Quote:

- You shouldn't have a groundplane under the AC entry point and the diode bridge. It can only couple noise and do no good. At least cut away the bit around the ac entry and around the AC pins of the bridge.

 
This makes sense, and will be done.
Quote:

- I would bring R5, R6 closer to the opamp pin: flip C4 by 90° clockwise and they can go down a bit.

 
They can only go down a fraction.  I'm spec'ing C4 to be up to 10mm/5mm LS.  The outline you see is the smaller 8mm/3.5mm option. 
 
And I don't see the purpose in rotating C4.
Quote:

 
Edit: I think you have room to implement remote sensing. You have to see if you want that feature or not. If you do, you have to link both the power supply and the ground to the sensing section by jumpers.

 
Not a lot of room to do this.  But it would be a nice feature to have.  I'll see if it'll work
 
 

 

[00940]

 
Quote:

Looking at the both tangents and Jung's work, it seems that this path on the regulator goes to the the Control ground or directly to the central "star" ground.  There is small and logical versus putting the ground of this reference path to a noisier area of the board.
 

 
In Jung's work ( http://waltjung.org/PDFs/Improved_PN_Regs.pdf , fig 1 and 3, same here : http://waltjung.org/PDFs/Regulator_Excels_In_Noise_and_Line_Rejection.pdf ) that goes to the input gnd (and he uses a looong track for that). Current goes back to C3 groundlead anyway, no reason to have it running all around the pass transistor. With the modulated opamp return ground currents passing by the same place, it isn't the quietest area of the board anyway.

 
Quote:

And I don't see the purpose in rotating C4.
 

 
Brain fart... I don't know why I thought for one second that you had your opamp on the bottom side. 

 
Stupid question.. don't you have enough room for putting back a DIP opamp ? To be in line with the through hole approach.

 

[cobaltmute]

On the second PDF you link to, it goes to the base of the op-amp in the schematic, but on the first link it does go to the base of the filter cap.
 
I'm going to keep it where it is - for now.  I see this as a trade-off in where the return current is going versus the possible advantage of having a bit of screen under this portion of the board.
 
As for moving back to DIP for the op-amp, it is possible.  However, given the fact that the op-amp I'm looking at is easier to get in SOIC versus DIP, I'm going to stay with SMT for the time being.