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Discrete R2R DAC

post #1 of 13
Thread Starter 

 

It's time for a reality check.

16 bit I2S discrete R2R DAC.

 

Does this look like it will work?

Any mistakes?

 


I don't expect spectacular sound quality, it's really just a learning toy.

 

The XOR decides if it listens to left or right channel data.

The rest is just a 32 bit shift register.

post #2 of 13
Thread Starter 

 

Hey, I thought of another use for this...

Get rid of the R2R ladder and replace it with LEDs.

Should make an interesting display...

post #3 of 13
Could you explain the operation of the circuit please Avro_Arrow? What is the format of the data? I'm kind of expecting 16 bits*2, which, yes would give 4 shift registers, but they would be paired into 16-bit outputs, each with it's own resistor network. Stereo DAC.

Fred
post #4 of 13
Thread Starter 

Circuit description:

 

 

Lets start with Left and Right channel selection.

 

The circuit shown is for just one channel.

The other channel is identical.

 

The L/Rclk signal lets us know which channel is being transmitted.

We are inputting an I2S signal and for that, when L/Rclk is low,

the Left channel is being transmitted and when L/Rclk is high,

the Right channel is being transmitted.

 

By using a 2 input Exclusive OR logic chip, we can select the

correct data. When both inputs match, either high or low, the

XOR makes its output low. If the don't match, the output is high.

In the circuit, we can select one input to be either high or low with

a jumper. When the L/Rclk signal matches the jumper, the XOR

output is low.

While the output is low, data can be clocked into the shift registers.

 

Now for the shift registers.

 

The shift registers clock in data when the output of the XOR

is low, and present it on their outputs when the XOR goes high.

For each "word" (left and right data), the bit clock (Bclk) cycles

64 times (64 Fs). In order for MSB to end up in the same place each time,

we have to have a total of 64 shift registers (32 for the left, and

32 for the right. Also, I2S waits one cycle of Bclk before transmitting

the first bit of information, so you can't use the first shift register.

That is why in the circuit diagram, Qh on IC5 is not used.

The 74*595 have eight registers each, so four are needed.

 

Is that enough to go on?

 

The data sheets can provided detailed descriptions of the inner

working of the logic chips used.


Edited by Avro_Arrow - 4/25/14 at 6:41pm
post #5 of 13

This looks way more "digital" than what I am comfy with, but I always thought that the problem with discrete R2R DACs was getting the resistors to match to an appropriate tolerance to achieve acceptable linearity. 

 

Hope this site helps:

http://www.sonicillusions.co.uk/discrete_dac.htm

post #6 of 13
Thread Starter 
Quote:
Originally Posted by nikongod View Post
 

 I always thought that the problem with discrete R2R DACs was getting the resistors to match to an appropriate tolerance to achieve acceptable linearity. 


Quite correct.

 

That's why I say this is pretty much just a toy.

Kinda like the DAC version of a CMoy...

 

I was going to use a Wheatstone bridge to match a bunch of 0.1% resistors.

It still won't be enough for good performance, the shift registers have internal

impedance as well.

post #7 of 13
OK, thanks. I had no idea that I2S has that wasted bit, and I thought it was 24-bit. Actually I thought it was capable of running with only 16 bits when that was all that was being used.

w

1000 posts!
Edited by wakibaki - 4/27/14 at 9:52am
post #8 of 13

Interesting stuff! I might play around with something like this soon.

 

Is there a particular reason you chose to design around that shift register model?

post #9 of 13

You could have inspiration here: http://easyaudiokit.hobby-web.net/bekkan/manual/RenewSimpleR2R.pdf

 

It is in Japanese, but Google translator can handle it. :normal_smile :

post #10 of 13
Thread Starter 
Quote:
Originally Posted by jgazal View Post

 

You could have inspiration here::normal_smile :


They have a much more complex front end to just end up with the same thing...shift registers feeding an R2R ladder...

post #11 of 13

I have promised not to post in technically oriented threads since I do not have the knowledge. I was just giving you a reference. He used to have other board. This is the sequence of development:

http://easyaudiokit.hobby-web.net/bekkan/new-R2R/new-r2r.html (old board)

http://easyaudiokit.hobby-web.net/bekkan/new-r2r-2/new-r2r-2.html (old board)

http://easyaudiokit.hobby-web.net/bekkan/FN1241/FN1241.html (new board)

If you look at his projects, he has tried almost everything.

I hope it is somehow helpful to you.

Cheers.


Edited by jgazal - 4/28/14 at 5:56pm
post #12 of 13
Quote:
Originally Posted by Avro_Arrow View Post

The shift registers clock in data when the output of the XOR
is low, and present it on their outputs when the XOR goes high.

Doesn't that mean that the outputs are updated out of phase by 50% of lrclk? I think you can just cascade the shift registers, get rid of the XORs and run the update of both left and right direct off lrclk. It's just a question of which is left and which is right, top or bottom. You might have to invert lrclk.

One of the things I'd build into an experimental prototype is the capacity to control the output pulse width. The chip has tristates, you could drive them using a one-shot run off lrclk.

w
Edited by wakibaki - 4/29/14 at 12:15pm
post #13 of 13
Thread Starter 
Quote:
Originally Posted by wakibaki View Post


Doesn't that mean that the outputs are updated out of phase by 50% of lrclk?
w


Yes, they are out of phase by 1/2 Fs.

 

Yes, you could cascade 64 shift registers and output them all at once.

 

Here is a diagram of an I2S signal for everyone following along:

 


I will have to look at the datasheet for the 595 when I get some time

to see how it would work.

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