So in order to fix this jitter on the I2S signals we “reclock” them with a flip flop clocked by the master clock. BUT the signals going into the flop also cause ground plane noise with a spectrum related to the jitter on the inputs, AND some of the transistors inside the flop are also switching based on the input signals, adding to the ground plane noise correlated to the “jittery” inputs. So why bother reclocking? It DOES decrease jitter, it just doesn’t eliminate it. If the I2S signals have quite a bit of jitter, the reclocking can cut it down by quite a bit, but there is STILL jitter on the output that is correlated to the input jitter AND there is noise on the ground plane related to the input signals that can influence the clock, clock mux, and DAC chip. So while reclocking can help, it is not a panacea.
So now the crux of the matter, how can what goes into the USB receiver affect any of this? In several ways: packet jitter, edge jitter, PLLs. I’ll go over each of these.
Packet jitter is the difference in the arrival time of packets to the receiver chip. USB packets are transmitted over the bus at either 1000 per second (full speed mode) or 8000 per second (high speed mode). Every time one of those packets hits the receiver a lot of activity happens inside the receiver chip. This creates lots of noise inside the chip and on the ground plane. This causes a lot of jitter on the outputs from the chip. The spectrum of this noise and jitter has a VERY strong component at either 1KHz or 8KHz, both of which are directly in the audio range. Any changes in the arrival time of the packets will change the spectrum of this packet noise. In the next installment I’ll cover what causes this packet jitter.