What's wrong with the capacitance multiplier - and how can it be improved

Intro: since this post is quite long, I'd like to sum this up in a sentence. This post shows an issue with the operation of the well known capacitance multiplier under appreciable load condition, with some background and simulation result as well as measured data. A solution to the problem is presented with some more simulation + measurement data for comparison - as well as a rule of thumb for selecting the right parts for your needs. </intro>
 
I want to share something I've noticed quite a long time ago - but up until now I was too lazy to sit down and write
Many PS designs use the capacitance multiplier as a LPF at the input to generate a clean DC supply for the error amplifier. The simple idea is to make a small capacitor act as a much larger capacitor by utilizing the fact the BJT follower has an output impedance which is ~hfe times lower than the impedance present at its base (and an additional re, which is usually very small and can be neglected).
 
However, there's one problem with this topology, which seems like many designs don't really take into account. Have a look at this simple circuit:


It a basic voltage regulator, with the input from the diode bridge on the left side, a capacitance multiplier for the error-amplifier, a pass transistor (in this case a BJT, but can be an MOS), and a voltage divider at the output for setting the DC voltage. The reference isn't shown, just for simplicity. Under the conditions shown here the capacitance multiplier will work just as expected. However, once we start sourcing appreciable current at the output, the voltage across C1 will flactuate quite significantly - the exact value of the "appreciable" current will depend on the capacitance at the input of the regulator (C1). The problem with this is that the assumptions under which the capacitance multiplier model was derived, are no longer true - even though the regulator itself still holds regulation as the voltage across C1 is higher than Vout+dropout voltage. This is no longer a circuit which can be approximated by a small signal model. If you look at the voltages at the terminals of T1 under these conditions it might saturate, and might even work in reverse polarity (VCB<0V).
Here's the VCE(volts) and IC(mA's) of T1 for this circuit with a 3300uF C1, 1K+100uF LPF, and a load of 1A (the results are from pSpice with the error-amp is biased at ~10mA):

As can be seen the transistor conducts in both directions, so the assumption it acts as a simple capacitance multiplier doesn't hold.

However, in some cases it can indeed be very profitable to use this circuit, and when it works as expected it improves performance significantly. This issue is actually quite easy to fix with the addition of 2 parts:


The addition of D1 and C4 solves the problem. Under no load it just adds an additional diode drop to the dropout voltage of the regulator (so it would be best to use a low Vf diode like a schottky diode to minimize this effect). However, under high load condition where the voltage over C1 changes significantly, correct selection of C4 will prevent reverse polarity of the transistor, and will allow the capacitance multiplier to act as we assume it acts. The correct value should be selected according the the line frequency (50Hz/60Hz) and according to the current the error-amplifier draws. The transistor T1 can operate in the forward region with VCE>0.2V, so we can allow ~0.5V of droop over C4. For instance in this example with a 50Hz input (100Hz after rectification), and 10mA in the error-amp we'll need C=I/(2*Frequency*0.5)=I/Frequency=0.01/50=200uF. Obviously using a higher value of capacitance won't hurt.
Here's the same simulation with these parts added to the circuit:

As you can see, the transistor now acts exactly as we'd expect it would, which would of course improve regulation significantly.

I've also measured that on the PS I use for my headphone amplifier, so I'll be able to post some measurement data. The test was done with the only regulator I own that uses a capacitance multiplier - the output voltage was set to 24V (23.3V) with a load of ~1A (15R+8R 50W resistors in series). Measurement was done with tangent's LNMP -> Agilent U1253A (recently calibrated). This measures from 5Hz-100KHz (-3dB), and scope images were taken with the DS1052E. I'd rather not state the regulator I've used because it was designed by another member, and because this issue would be identical for all regulators that use this scheme, so the exact model is of little importance. Here are the results:
regulator with no modification:
Output noise: no load - 11uVRMS    1A load - 107uVRMS
Here's VCE of Q1 under these conditions:
No load:

1A load:
 
As you can see, VCE is consistent with the simulation results with a significant AC component, and goes all the way down to 0V which means the capacitance multiplier isn't operating as expected.

regulator with proposed modification (UF1004 diode + 330uF cap (these are the closest value I've had at the moment)):
Output noise: no load - 11uVRMS    1A load - 83uVRMS
And the VCE of Q1 under 1A load:

 
Which again is the same as in the simulation results, making sure the transistor stays in the same mode of operation - this also yield an improvement in the output ripple due to the lower ripple in the supply voltage of the error amplifier.
 
I've modded my regulator to include these parts and left it that way, even though under the low current I usually use with my headphone amplifier it makes no difference. Hopefully this will be helpful for other HF readers as well.
 
Edit: I've added some additional info which shows another benefit of this circuit in post #4 of this thread.
 
Edit2: Ti (AMB) did some measurements of what I've shown here as well, and he's results are quite similar to what I've found here. You can read he's original post here.

Thanks for the info.
 
In the original, what would happen if you drop a zener diode for the appropriate voltage, in parallel to C2 and a cap (to ground) at the output of T1?

1. There's always a cap at the output of T1, I just left it out for simplicity. I'm not sure I've even seen someone implement it without this cap.
2. If you add a zener in parallel to C2 you are really wasting C2. A zener has a very low small-signal impedance so the cap will have little to no effect if the zener is operating as expected. So basically the zener and C2 try to do the same thing, keep this voltage constant by presenting a very low impedance (in the case of the cap its just to AC signals, in the case of the zener its for all signal once the zener is properly biased). The real issue with the zener is that it eats up a lot of current (mA's) so you'll have to use a very low value for R1 to keep the dropout voltage acceptable, and the fact it'll require the voltage across C1 to always be high enough to keep the zener biased. So in effect it'll increase the dropout too much for it to be any good. So to sum it up, personally I would advice against it
 

I would like to point out another gain of using this circuit with the modification, which might not be visible at first sight. Even though the dropout of the regulator is increased by another diode drop for a DC input, this isn't the case in real world situation. Since in practice the input voltage (across C1) will drop significantly between charges from the rectifier, this circuit modification will actually allow the voltage across C1 to drop lower without affecting regulation.
 
The reason for that is the following:
The limiting factor of the dropout voltage in most designs is the path from the output to the filter cap (C1) through the control node of the pass transistor (base-emitter drop of T2 in the schematics above), through the error-amp (minimum difference between VCC and the output voltage of the error amp), through the input filter to the supply of the error-amp (the capacitance multiplier in this case). The voltage across C1 must remain above the output voltage + the minimum required voltage for correct operation of this path during the entire cycle.
 
In the presented circuit (with D1/C4 included), this limitation is lifted. The voltage across C1 can drop significantly lower (down to VCEsat above the output voltage in this case, and down to Vdsat above the output voltage for an MOS pass-transistor), and the voltage across C4 will still remain within 0.5V+diode drop below the maximum voltage attainable across C1 (which is usually secondary voltage of the transformer*1.4 - 2 diode drops).
 
I did some simulations to verify this, and with the same circuits I've used for simulations in the first post, this raised the maximum attainable output current with a 3300uF for C1 from a value of ~1A to ~2A with an output ripple of 1mVpp. So in practice this will allow a much higher currents from the same input capacitance value.
 
BTW, this trick can be used even without the capacitance multiplier. Just add D1+C4 (and select the value of C4 according to the procedure in the first post), and now the voltage across C1 can drop to Vout+saturation voltage of the pass transistor at its lowest value.