Power supply loop bad?
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DCameronMauch

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Playing around with a board layout. Basically a four channel balanced output PPA but with single ended pure class A mosfet buffers instead of a pile of HA5002s. It is very convenient for me to have both rails circle around the entire board. Positive on bottom, negative on top. But is having a power supply loop a bad thing? If so, why? Here is a picture of the board so far. Thanks!
 
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Tomo

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Hi,

Can you post schematics for me? The exact one.

Single MOSFET Class-A stage are more difficult to play with than HA5002 or any other buffer chips. I am a bit worried how they are biased.

Tomo
 
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DCameronMauch

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Hello. Sure. Here is one side. The schematic does not show the complexity of the current sources for biasing the opamps. But we all know what those look like. Two fets, one resistor, one pot. The output stages are biased with 100mA constant current. Just a tad over 1mA flowing down through the TL431A. I found that a bypass of 5pF around the opamps nicely supressed a nasty gain spike out around 30MHz. Total voltage gain 5x (2.5x per phase).
 
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kwhead

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Yes, that's bad, you don't want a loop on either power or ground. Break both loops somewhere so that you have a C (or Y) shape. Never a loop. It would also be best if it was broken such that the left channel was on one branch and the right channel on the other to reduce cross talk through the power trace impedances.

The reason you don't want any loops is that they will couple enourmous amounts of electromagnetic interference onto your power supply rails since you've built a loop antenna. This is mostly high frequency (near RF) and bypass caps do absorb a lot of it. However on your layout I only see big caps which will do little or nothing to attenuate RF noise, you'd need to throw in some low value ceramics in parallel to do that (0.1uF ~ 1uF).

At lower frequencies (audio) the loop doesn't respond so much to EM fields like an antenna but rather directly to just the alternating magnetic field. Acts like a really crappy transformer. This will generate time varying potential differences all along the loop proportional to the external field. Pretty much anywhere in your house there is a strong 60Hz power line field and a rich set of harrmonics pushing well above 1kHz. Power and ground loops beg for an amp to hum. If everything is just right, your ears are good enough, and your TV sucks you can also be treated to 15kHz vertical sync interference. Most amp's power supply rejection ratio drops quickly with frequency, so even though this signal may be lower than 60Hz power line noise the amp is more susceptible to it.

Of course, you can always build the amp as is and if you have an interference problem cut the loop by hand. But you aren't really buying anything with the loop and its trivial to break now, so I'd do that.
 
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tangent

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Two thoughts:

- We got away with a ground bus loop on the META42, but that was a much smaller board.

- Your output stage doesn't look like it would have much PSRR at all.
 
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DCameronMauch

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kwhead: I gave your comments a lot of though. I think you are completely correct. You talked me out of it. Reminded me of that rule about never having a conduction path through the center of a transformer. Forgot about that one. Now those big caps are just the beginning. Even then I intend to use Black Gate N series in the "super-E" configuration. Which is also why I made sure there were an even number of caps on each side. Planned on soldering .47uF B.G.N.s right onto the power supply pins of the opamps. Nearby would be a 10uF, some fets for isolation, and another 10uF (just like the PPA). For each individual opamp. These other power supply features are not shown on the board layout yet.

tangent: Yeah, the PSRR of the output buffers is quite low. Fortunately they are wrapped around by the opamps. And those will use the fet isolation like the PPA. So the total PSRR shouldn't be too bad. As for the power source, I plan to have two +-12Vdc inputs. A front panel switch to select which one is feeding the board. One would be a decent wallwart type to keep the unit continuously warmed up. But when I want to listen, I would switch over to some big honkin' lead acid batteries. That should help out the situation too. What do you think? Does this kind of setup sound good to you?
 
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DCameronMauch

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Just did some PSRR simulations for the single ended class A output buffers ALONE. Not as bad as I thought it would be. At 1kHz, the PSRR is around 62dBV. Around 45dBV at 100kHz. Gets worse linearly on a log/log graph. PSRR totally fails around 30MHz. BUT... This is for just for a single phase! This is a balanced (dual phase) output. If we are talking PS ripple, common to both phases, the PSRR goes over 120dBV at 120/240/480Hz. As for pure random noise. I remember a long time ago from a white paper on paralleling DAC chips. Doubling up a given source (with a noise component) gives you a 6dBV signal gain, but only a 3dBV noise gain. So even in the case of pure random noise, SNR is improved by 3dBV. Then, when you wrap each buffer around with an opamp, things get even better. I also chose the IRLIZ25N mosfets because of all the mos spice models I have available to me, these gave the best THD graphs in the stand alone buffer configuration. Thus making the opamp's job that much easier when driving the buffer.
 
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DCameronMauch

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kwhead: Here is what the board looks like today, based on your feedback. Still lots of stuff to put in there...
 
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