New Audio-gd R-7, R-7HE R-8, R-27, R-27HE, R-28 Flagship Resistor Ladder DACs and DAC/amps
Mar 26, 2022 at 5:21 AM Post #8,446 of 11,225
Friends, in search of a solution, I switched the Xilinx blaster to another module inside the device, and the firmware loaded! But the instructions say that there are two modules inside the device, but it is impossible to update the second one for the reasons mentioned earlier. http://www.audio-gd.com/R2Rupdate2.htm. Or does this not apply to audio gd r7 he mkii, and my device only needs to update one module?
 
Mar 26, 2022 at 7:13 AM Post #8,447 of 11,225
Xilinx is not an easy task at all! But after many repeated attempts, it was finally possible to update both modules! however, the iis signal disappeared... Everything is fine at the optical input. Of course, while I was programming, I connected and disconnected the device several times, I don't understand what could have happened, or I have to return the old firmware for verification... Has anyone ever had such a problem?
 
Mar 26, 2022 at 8:07 AM Post #8,448 of 11,225
@Raul77 At least you are making progress! Lets back up. Which upgrade are you trying to apply? Reason for asking is the "two modules" illustrated in the document above are the DA modules on the R8.

For the R7 MK2 and PLL_N firmware upgrade you only program one Xilinx on the middle, digital board and the Altera from the backpanel port. The other Xilinxs do not require upgrading. See below for the PLL_N Xilinx JTAG header location.
 

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Mar 26, 2022 at 8:29 AM Post #8,450 of 11,225
With your help, things are really moving forward)) Firstly, I updated the upper module in the photo, but the k7 ru mkii audio saw stopped seeing the clock. Then I updated the second module and the sound from iis disappeared, but the clock appeared. With AES and optics, there is sound....
 
Mar 26, 2022 at 8:51 AM Post #8,452 of 11,225
@Raul77 In the link below is the Xilinx code for the 2nd Xilinx port "IIS_pro.jed". This file will restore I2S operation. Program this code from the bottom connector in your picture. And to clarify keep PLL_N Xilinx upgrade on the "top JTAG port" and reprogram the bottom port "II2_pro.jed". Reboot the DAC after upgrading. If this works OK you are now a Xilink programming expert!

(This information is incorrect. See 5 posts below for correct file to use)
 
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Mar 26, 2022 at 8:57 AM Post #8,453 of 11,225
The programming of the module on top likely failed. It seems.

[edit] but since the clock works, leave it as is and test after reprogramming the bottom one.
 
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Mar 26, 2022 at 1:05 PM Post #8,457 of 11,225
The R7 MK2 I2S Xilinx file posted above is not correct. So I copied my working R7 MK2 I2S Xilinx code to a jedec file. You only need to program the I2S Xilinx if you screw up and misprogram the wrong Xilinx during PLL_N upgrade on the R7 MK2s.

The R7 MK2 I2S Xilinx file name is "R7MK2_IIS_Default.jed".
To clarify the PLL_N upgrade only needs the clock select Xilinx CPLD (JTAG port documented) with "clk_sel_R7MK2_PLL_N.jed". And the Altera FPGA updated with "R7MK2_PLL_N.jic"

https://onedrive.live.com/?id=636DC4E8060D66A1!561&cid=636DC4E8060D66A1
 
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Mar 28, 2022 at 10:30 AM Post #8,459 of 11,225
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