Quote:
Originally posted by Traveller
Now we are getting somewhere (thx, Juergen) |
Ok, some initial details (& plz keep in mind, I'm EE-impared!).
The first (& most obvious) assesment is that there are some redundant circuits between the core
Motorola Coldfire processor & the
Philips Audio Coder-Decoder chips
(not to mention the separate Ti ADC chip!).
But here's a few
assumptions on my part. They are based on the extremely detailed documentation Philips provides (s/b available @ Juergen's
iHP Lounge).
I'm guessing that the Coldfire is only responsible for decoding audio files at which point the digital datastream is sent to the Philips Audio chip (via Data-in). The Coldfire also sends commands to the Philips chip (via the L3/ [ed. I2C, not I2S] interface).
The Philips chip is responsible for all audio I/O (as seen by both the block diagram & PCB traces). ADC, DSP processing, etc - could be performed by
either chip, but I'm betting again Philips' is doing the work. The Coldfire chip looks like a CPU with a few built-in goodies that on a typical PC would be done by either peripheral HW or by SW.
While the Coldfire has, for example, an ADC component, I think that it's there to spare the [portable] designer the need to add extra chips (lowering costs) but the quality will certainly be lower than
dedicated audio chip(s).
The key components of the Philips chip are:
Analog & digital [ed. I2S] i/o, gain ("PGA" - Programmable Gain Amp), A/D + "Decimator", DAC components (Interpolation filter, Noise Shaper (5th order) & "Filter Stream" D/A, amps), and finally, a headphone-driver "stage".
Possible data paths
HDD->Coldfire (decoded, perhaps complex DSP routines,...) -> Philips (Din, additional DSP, Interpolation Filter, Noise Shaper, FSDAC, Vout -or- HP Driver -> VoutHP)
Philips (Vin @12KOhm, PGA, ADC/ Decimation Filter/ DC-Cancellation Filter), DSP-optional, Dout) -> Coldfire (encoding) -> HDD.
Those are two possible paths. There are many others, considering the iHP-120 has Line-in, internal-Mic-In, External-mic-in, S/PDIF-in, Line-out and S/DIF-out.
There are also different analog (i/p signal) gain "stages" depending on i/p-type (eg. Low-Noise Amp w/29dB gain for mic), Vol Ctrl can be performed in the [ADC] Decimator "stage" (+24dB, -63.5dB) and again in the Interpolation stage (0, -78dB max suppression).
The 1-bit DAC ("Filter Stream DAC") is designed to provide low-clk jitter and has "on-board" amps to drive the subsequent stages (Vout, HP Driver). This stage also provides a form of filtering that eliminates the need of an external filter on the o/p side.
The HP Driver "stage" can o/p 35mW into 16 Ohms (given a 3.0V supply) and is designed to eliminate the need for external caps (DC-coupling).
Last but not least, the FSDAC stage can accept analog signals (which are "forwarded" to the next stages) and this is (most likely) how the iHP's FM signals are sent to the Vout & HP Driver.
Again, I am basing my assumptions on Philip's documentation: how iRiver uses the chip's functionality is still an unknown variable, but I think my assumptions are reasonable. I would be more than pleased if someone with an EE background could back up or refute the assumptions made so far
But if nothing else comes of this amateur analysis, some of the more simple questions asked by myself and other posters here (such as what is the difference between Line-out & HP-out) have been answered...