Clock distribution IC?

[Crowbar]

Anyone know of a clock buffer/distribution chip with very low additive phase noise? < -115 dB at 10 Hz offset. I thought of using AD9510 but it's very complex, needing programming internal registers, and has a bunch of crap on it I don't need so it's a waste of money too.

Clock I'm feeding it is the usual 24.something MHz.

 

[threepointone]

Did a whole crapload of resesarch on this before. I think Maxim has a whole bunch of them, but the biggest problem I had was figuring out exactly how much phase noise/jitter there was--everyone seems to measure it differently, and I think most of them don't measure even close to the 10Hz range since most applications that actually need low jitter aren't sensitive at all to that frequency. Unfortunately I kind of refocused my attention to some things outside of audio halfway through, so I can't tell you much about how to actually implement it or what ICs will work =(.

IIRC don't bother with the Cypress clock distribution ICs--they all have enormous jitter. Look for the ones designed for very high speed fiber optics and other high speed data links. I have to say though, it's pretty hard to find an IC without a lot of features you don't need. Also remember that the distribution IC needs to be capable of pretty low frequencies (most of these are normally used with at least a couple hundred megahertz)--preferably you don't want to have to bother with a clock divider, since that probably adds phase noise and might get different clocks (if you're using it for distribution) to have relative phase noise.

quick disclaimer: might be wrong on a couple of things up there, since I haven't gone back to this in at least a couple of months

 

[Crowbar]

The thing is, the distribution is basically a multi-output buffer. I wonder if I might not get good enough performance just using some picogate buffers in a bifurcating configuration (I think one output to two inputs is about right, or maybe three is still OK for a branching factor). I suppose I could ask the clock manufacturer to make a recommendation.

Eventually I managed to get data from TI on the CDCV304, which is a bare clock buffer. However, the graph was a comparison of the clock's phase noise vs the through-buffer phase noise. Since their test clock was already high jitter (-75 dB at 10 Hz offset) I couldn't reasonably extrapolate what would happen with my intended clock with phase noise at < -105 dB at 10 Hz. I asked, and the reply seemed to be carefully worded:

Quote:

CDCV304 is one of our best buffers in terms of phase noise performance. The output very closely follows the input clock phase noise. And you have seen from the plot which we sent you earlier. The signal sources we have don’t have phase noise performance like TCXO (especially close to carrier). But we expect similar performance even with -105 dBc/Hz at 10 Hz input clock. I can’t tell you the exact number at 10 Hz, but output clock will have pretty close to -105 dBc/Hz at 10 Hz.

The way I take it is that it will probably be fine, but to be sure I need to measure it. Which, of course, means I have to figure out how to measure it and I don't even have a spectrum analyzer...

I was looking at Techniques for Measuring Phase Noise but it's going to take some building...