kelowna said:

  I'm just clearing up some BS with facts that's all. And I was never banned from this forum. Here's another fact. the LM723 LDO is only rated at 2.5uV noise from 100hz to 10K. the PSRR is a decent 86dB, however it's only a 150mA LDO. So only useful for very low voltage applications. The $54 Belleson's have a noise rating of 1uV, PSSR throughout the entire audio bandwidth of -110dB, and can handle 2A current.  

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kelowna said:

  Ted Smith's take on external clocks. Skip to the 3:40 for the part about External clocks. 
 
 

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rb2013 said:

Why do bother to post this stuff here - none of the DDC's have ext Wclock inputs.  Why not post over on my Rednet AOIP thread?  It has a Wclock input.  Unless you were/are banned there...http://www.head-fi.org/t/806827/audio-over-ip-rednet-3-16-review-aes67-sets-a-new-standard-for-computer-audio

Anyway - I could give a Schiit what some gray bearded test bench jockey says about OXCO ext Wclocks - I have heard with my own ears - the same ones that discovered the F-1 and started this thread (and the Rednet AOIP thread).  Ext Wclocks make a difinite difference.  On the AOIP thread - many, many others have had the same experience.

Bet old gray beard thinks all cables are the same...

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carlmart said:

  rb2013
 
What about the sonic differences between the X1 XU-208 and the F-1 XU-208?
 
What DAC are you linking these boards to? Through I2S?

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tboooe said:

  Thank you for the reply.  So am I understanding you correctly...the F1 powered by a good source is better than Mutec 3+USB even with its reclocking feature?  If this is true I would love to sell my Mutec to free up some cash and get more audio goodies I've been considering.
 
Agreed.  I got mine used on ebay for $100.

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kelowna said:

What was the phase noise of the internal clocks you compared the external clocks to? Without knowing that, it's not much of a revelation. It should be a given that a $1000+ external will outpreform a 39 cent crystal powered by a $2 SMPS.

I priced out the Ferex SMPS's in the Rednet 16 and they cost $1.80 a piece in quantities of 1000 pieces. Ripple noise is 150000uV RMS, (likely double P-P). So even if they use the world's finest LDO's the internal clocks aren't getting very clean power. Even with run of the mill clocks, ultra clean power is required to meet phase noise spec of the crystal.

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kelowna said:

@Rob

I would get your buddy Alex to send you some if his -112dBc @ 10hz phase noise Crystek 575's, to replace the clocks in the Rednet. Then ditch the $2 SMPS and replace with a Daitron/reg board combo and for under $400 I can assure you you'll be able to ditch the external clock and reclocker and still get better sound.

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rb2013 said:

Sorry my ears don't need or care about test bench measurements.

Internal clocks were excellent XO's - the OXCO is orders of magnitude better then the best Crysteks.

That is good info on the Rednet gear - yes they use cheap SMPS - no mystery solved there.  I agree most Pro Audio gear (like the Mutec MC-3+) use SMPS power supplies.


The reason we have pulled the SMPS on the BURL B2B DAC and replaced it with a LPS.

I really like the fact the new Antelope Liveclock has an ext DC power input...I used the older OCX which has a SMPS.

But if you want to run test bench measurements against each other - if THAT'S what matters to you engineering types then:

It not just phase noise  - but clock stability that matters.  XO's and TXCO's drift away from their ref freq over time:

From the CCHD957 datasheet:
Aging: +-3ppm first yr, +-1ppm/yr there after...

OXCO (like the Abracon):
Aging:  +-100ppb, +-.5ppb/yr there after.

Oh as for Phase noise:

957 @10Hz: -100dbc
OXCO@ 10Hz: -120dbc

So let's see a OXCO is orders of magintude more stable (both short term and long term) then the CCHD-957, but also has -20dbc less phase noise at 10Hz. 
That's about 100 times less.

Oh NOW my ears can hear the difference - since the test bench proves it!  Eureka

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rb2013 said:

I guess you are to busy talking to listen - or read - what I just wrote.  I sold the Rednet.

While you are fiddling around with your SD card reader and $1700 streamer...I already have a one box (well two if you count the ext LPS) AOIP solution...and I bet it blows away that stack of boxes you have.

DAC/AOIP Ethernet - all in one tidy package!

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kelowna said:

The problem with your testing is you are comparing a much better clock in the external to crap clocks in the internal. There's no advantage to putting the clock in a seperate box, generating a PLL, sending over cable, then going into the DAC. Placing a clean crystal very close to the DAC chips will blow it out of the water. The guys who manufacturer the gear you like also know this. This is because they are engineers who know what matters.

All of this talk of long term stability is meaningless. Because you don't have a solid reference of comparison.

Perhaps you should talk to this guy:

https://by-rutgers.nl

Knowledge is not a handicap if it's accurate

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2.1 Period Jitter Period jitter is the deviation in cycle time of a clock signal with respect to the ideal period over a number of randomly selected cycles. If we were given a number of individual clock periods, we can measure each one and calculate the average clock period as well as the standard deviation and the peak-to-peak value. The standard deviation and the peak-to-peak value are frequently referred to as the RMS value and the Pk-Pk period jitter, respectively. Many publications defined period jitter as the difference between a measured clock period and the ideal period. In real world applications, it is often difficult to quantify the ideal period. If we observe the output from an oscillator set to 100 MHz using an oscilloscope, the average measured clock period may be 9.998 nS instead of 10 nS. So it is usually more practical to treat the average period as the ideal period 

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2.1.2 Calculating Peak to Peak Jitter from RMS Jitter Because the period jitter from a clock is random in nature with Gaussian distribution, it can be completely expressed in terms of its Root Mean Square (RMS) value in pico-seconds (pS). However, the peak-to-peak value is more relevant in calculating setup and hold time budgets. To convert the RMS jitter to peak-to-peak (Pk-Pk) jitter for a sample size of 10,000, the reader can use the following equation: Peak-to-peak period jitter = 7.44 x (RMS jitter) Equation 1 For example, if the RMS jitter is 3 pS, the peak to peak jitter is ±11.16 pS. Equation 1 is derived from the Gaussian Probability Density Function (PDF) table. For instance, if the sample size is 100, 99 of those samples will fall within ±2.327σ from the mean value of the distribution, only 1 sample, on average, will fall outside that region. SiTime measures the RMS period jitter over a sample size of 10,000 as specified by the JEDEC standard. Sample Size Sigma (σ) 10 ±1.282 100 ±2.327 1,000 ±3.090 10,000 ±3.719 100,000 ±4.265 1,000,000 ±4.754 10,000,000 ±5.200 100,000,000 ±5.612 1,000,000,000 ±5.998 10,000,000,000 ±6.362 100,000,000,000 ±6.706 1,000,000,000,000 ±7.035 Table 1. Gaussian probability density function (PDF) 2.1.3 Period Jitter Measurement Methodology Period Jitter is defined in JEDEC Standard 65B as the deviation in cycle time of a signal with respect to the ideal period over a number of randomly selected cycles. The JEDEC standard further specified that period jitter should be measured over a sample of 10,000 cycles. SiTime recommends measuring period jitter using the following procedure: 1. Measure the duration (rising edge to rising edge) of one clock cycle 2. Wait a random number of clock cycles 3. Repeat the above steps 10,000 times 4. Compute the mean, standard deviation (σ), and the peak-to-peak values from the 10,000 samples -------------------------------------------------------------------------------------------------------------------------------------------- The Smart Timing Choice™ 4 SiT-AN10007 Rev 1.2 Clock Jitter Definitions and Measurement Methods 5. Repeat the above measurements 25 times. From the 25 sets of results, compute the average peak-to peak value. The standard deviation (σ) or RMS value computed from a measurement of 10,000 random samples (step 4) is quite accurate. The error in the RMS value can be calculated using the following equation: ErrorRMS N n 2 σ = Equation 2 where σn is the RMS (or sigma) of the collected sample and N is the sample size. For a sample size of 10,000, ErrorRMS is 0.0071σn. This error is random and it follows the Gaussian distribution. The worst-case measurement error is typically computed as ±3 ErrorRMS. For example, if the RMS value computed from 10,000 random samples is 10 pS, then the ErrorRMS will be 0.071 pS and virtually all the RMS values of this measurement will still fall within a narrow range of 10 ± 0.213 pS. In practical applications, the RMS errors in a sample set of 10,000 are small enough to be ignored. While an accurate RMS value can be computed from a random 10000-sample set, the peak-topeak value is more difficult to measure. Due to the random nature of period jitter, the larger the sample size, the higher is the probability of picking up data points at the far ends of the distribution curve. In other words, the peak-to-peak value diverges instead of converging as more samples are collected. That is the reason why we added an extra step, step 5 to produce a more consistent and repeatable peak-to-peak measurement. Each measurement of 10,000 random samples (step 4) produces one standard deviation value and one peak-to-peak value. By randomly repeating this process 25 times, we could collect a good set of data points from which we can calculate the average peak-to-peak value with a high degree of accuracy. We can also compute the average RMS value from this data, but it will be very close to the RMS value derived from each individual run. Figure 3 is the period jitter histogram of a 3.3V SiT8102 oscillator running at 125 MHz captured by a Wavecrest SIA-4000C. It represents one set of RMS and peak-to peak values measured from 10,000 samples (step 4) 

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2.3 Long-Term Jitter Long-term jitter measures the change in a clock’s output from the ideal position, over several consecutive cycles. The actual number of cycles used in the measurement is application dependent. Long-term jitter is different from period jitter and cycle-to-cycle jitter because it -------------------------------------------------------------------------------------------------------------------------------------------- The Smart Timing Choice™ 7 SiT-AN10007 Rev 1.2 Clock Jitter Definitions and Measurement Methods represents the cumulative effect of jitter on a continuous stream of clock cycles over a long time interval. That is why long-term jitter is sometimes referred to as the accumulated jitter. Longterm jitter is typically useful in graphics/video displays and long-range telemetry applications such as range finders. SiTime recommends measuring long-term jitter using the following method; in this example, we measure the long-term jitter over 10,000 clocks. 1. Measure the time interval of 10,000 consecutive clock cycles as shown in Figure 5 2. Wait a random number of clock cycles 3. Repeat the above steps 1,000 times 4. Compute the mean, standard deviation (σ), and the peak-to-peak values from the 1,000 samples 5. Repeat above measurements 25 times. From the 25 sets of results, compute the average peak-to peak value. Figure 5. Measuring a 10,000 clock-cycle time interval Once again, step 5 is needed to overcome the un-bounded nature of the peak to peak value. 

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 Time Interval Error (TIE) Time Interval Error (TIE) of an edge is the time deviation of that edge from its ideal position measured from a reference point. In effect, TIE is the discrete time domain representation of phase noise expressed in seconds or pico-seconds. Figure 7 illustrates the basic concept of TIE. The ideal signal is often a signal created in software from an average estimate of the signal period. Figure 7. Measuring the TIE of an edge 3.1 Plotting TIE over time A clock waveform is shown at the top of Figure 8. The red pulses are perfectly timed clock cycles exactly 1000 pS in duration. The pulses in black are clock cycles with jitter. The trailing edges of these clock pulses have been removed to enhance the presentation. At the beginning of the sequence, both the red and black clocks are aligned to each other. Because of the jitter, the black clock edges will start shifting in time, sometimes occurring before the red clock edge and sometimes after. The plot labeled “Clock Period” represents the measured black clock periods over time. In this example, the black clock periods are either 990 pS or 1010 pS. The “Period Change” plot depicts each cycle’s change from the previous cycle. This graph remains flat as long as the period between two consecutive black clocks stays the same. However, it will register a change whenever a period difference is detected. For example, the period of the first 4 clock cycles are constant at 990 pS, so the “Period Change” plot is flat; but when the period of the fifth clock is lengthened from 990 pS to 1010 pS, the plot reports this change by jumping to the +20 pS position. In other words, this plot identifies the period changes shown in the “Clock Period” plot. T1 T2 Reference Edge Ideal Location of the edge TIE = T2 – T1 Actual Location of the edge Ideal Signal Actual Signal -------------------------------------------------------------------------------------------------------------------------------------------- The Smart Timing Choice™ 10 SiT-AN10007 Rev 1.2 Clock Jitter Definitions and Measurement Methods The “Time Interval Error” (TIE) plot documents the accumulated error between the ideal edge (red clock) and the actual edge (black clock). In this example, the TIE plot begins by moving towards the negative direction because the first 4 clocks are each 10 ns shorter than the ideal period. After accumulating -40 pS in jitter error, the plot changes direction at the fifth clock and heads towards the positive direction because the fifth clock period is 10 pS longer than the ideal period. TIE measurements are especially useful when examining the behavior of transmitted data streams, where the reference clock is typically recovered from the data signal using a Clock/Data Recovery (CDR) circuit. A large TIE value may indicate that the PLL in the CDR is too slow in responding to the data stream’s changing bit rate. Figure 8. Time interval error (TIE) plot

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rb2013 said:

No I just compared the Crystek CCHD-957 to a OXCO.

Oh so clock stability does not matter in computer audio? Huh.  What is the basis of computer audio but clocking?  A ref clock is just that a reference.

It's 24.576Mhz right - not 24.7 or 24.4.  So how important is clock freq stability?

Well how about phase noise - just showed the OXCO to be 100 times lower...

Here are some guys that know a little about audio clocks:
https://www.sitime.com/support2/documents/AN10007-Jitter-and-measurement.pdf

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An ideal DAC converts the abstract numbers into a conceptual sequence of impulses that are then processed by a reconstruction filter using some form of interpolation to fill in data between the impulses. A conventional practical DAC converts the numbers into a piecewise constant functionmade up of a sequence of rectangular functions that is modeled with the zero-order hold. Other DAC methods such as those based on delta-sigma modulation) produce a pulse-density modulated output that can be similarly filtered to produce a smoothly varying signal. 

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In mathematics, a function on the real numbers is called a step function (or staircase function) if it can be written as a finite linear combination of indicator functions of intervals. Informally speaking, a step function is a piecewise constant function having only finitely many pieces. 

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kelowna said:

Describe the DAC setup with the Crystek 957.

1: Did you have the clocks measured to confirm phase noise?

2: What was the noise level of the supply powering it?

3: Were there line drivers/ buffers used for LRCLK,Bclk and Mclk?

4: What was the digital interface used?

5: How is the clocking scheme implemented in the digital interface FPGA?

6: Does the digital interface FPGA use internal line drivers or external?

7: How long are the clock traces on the PCB?

8: Were there any connections in the clock traces, or PCB stubs?


I suppose that's a good start. However many more variables after those questions are answered

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rb2013 said:

https://en.wikipedia.org/wiki/Digital-to-analog_converter

https://en.wikipedia.org/wiki/Step_function




Any deviation in clocking from the expected reference produces time domain anomalies - these present as time period jitter distortions.

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kelowna said:

The clock and DAC engineers I know can answer my above questions in a clear concise manner.

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