A quick divergence from DIY electrostatic projects... working on making a DIY stereo smyth realiser (couldn't care less about any more than 2 channels, only listen to music - can get by with a lot less DSP than the 8-channel realiser needs).
Currently my hardware is a Digilent Nexys 4 dev board with an Artix 7 100T FPGA. Hard to beat for the price, 240 18x24 multipliers and 135 36kb RAM blocks. I built an add-on board which receives and transmits SPDIF and also has a stereo mic input amplifier and 24 bit ADC.
So far I've got all the IO systems setup for SPDIF and the ADC, and designed/tested 16384 sample 4-way stereo true-convolution (104gbit/s memory bandwidth, 2.9 billion 24x24 multiplies/s... aren't FPGA's awesome?)
Next up will be designing the room capture algorithm. This is actually not all that difficult in practice. Do a log sine sweep, record it, and perform ifft(fft(measurement)/fft(test_signal)) to get the convolution impulse. Actually implementing will be a bit of work since I'll need to manually code the FFT library using an external RAM chip to handle a 524288 sample FFT. Fortunately the dev board comes with a 128mbit RAM chip. I'll store the captured impulses on an SD card.
Ultimately I'll add a head-tracker too, but that's still a ways down the road. The hardware should be simple enough, just an accelerator on a wireless card. The software is not that bad either, I can stream a new kernal into the RAM buffer every few milliseconds in real-time while the convolution is operating.
More to come...